Cadence Digital, Custom/Analog Design Flows Achieve Certification for TSMC’s Latest N4P, N3E Processes
October 26, 2022 | Cadence Design SystemsEstimated reading time: 3 minutes
Cadence Design Systems, Inc. announced that TSMC has certified the Cadence® digital and custom/analog design flows for the latest TSMC N4P and N3E processes in support of the new Design Rule Manual (DRM) and FINFLEX™ technology. Through continued collaborations, the companies have also delivered the corresponding N4P and N3E process design kits (PDKs) to accelerate advanced-node mobile, AI and hyperscale computing design innovation. Customers have already started using the latest TSMC process technologies and certified Cadence flows to accomplish optimal power, performance and area (PPA) goals and speed time to market.
Latest N4P and N3E Digital Full-Flow Certification
The Cadence and TSMC R&D teams worked together closely to ensure the digital flow met TSMC’s advanced N4P and N3E certification requirements. Cadence’s complete RTL-to-GDS flow includes the Innovus™ Implementation System, Quantus™ Extraction Solution, QuantusFS solution, Tempus™ Timing Signoff Solution and ECO option, Pegasus™ Verification System, Liberate™ Characterization Solution, Voltus™ IC Power Integrity Solution and Voltus-Fi Custom Power Integrity Solution. The Cadence Genus™ Synthesis Solution and predictive iSpatial technology are also enabled for the TSMC N4P and N3E process technologies.
The digital full flow offers several key capabilities that support the TSMC N4P and N3E process technologies, including native mixed-height cell row optimization from synthesis to signoff engineering change orders (ECOs) for optimal PPA; standard-cell row-based placement; implementation results that are well-correlated to signoff for faster design closure; enhanced via pillar support for better design performance; large libraries containing many multi-height, voltage threshold (VT) and drive-strength cells; timing robustness cell characterization and analysis; reliability modeling using aging-aware STA; and CCSP model enhancements providing improved accuracy and simplified characterization for analysis via the Voltus IC Power Integrity Solution.
Latest N4P and N3E Custom/Analog Flow Certification
The Cadence Virtuoso® Design Platform—which includes the Virtuoso Schematic Editor, Virtuoso ADE Product Suite and Virtuoso Layout Suite—and the Spectre® Simulation Platform—which includes Spectre X Simulator, Spectre Accelerated Parallel Simulator (APS), Spectre eXtensive Partitioning Simulator (XPS) and the Spectre RF Option—have been certified for the TSMC N4P and N3E processes. The Virtuoso Design Platform uniquely provides a tight integration with the Innovus Implementation System, which augments the implementation methodology of mixed-signal designs via a common database.
The custom design reference flow (CDRF) has also been enhanced to support the latest N4P and N3E process technologies. The Virtuoso Schematic Editor, the Virtuoso ADE Suite and the integrated Spectre® X Simulator help customers effectively manage corner simulations, statistical analyses, design centering and circuit optimization. The Virtuoso Layout Suite has been tuned for efficient layout implementation, leveraging a row-based implementation methodology with placement, routing, fill and dummy insertion features; enhanced analog migration and layout reuse functionality; integrated parasitic extraction and EM-IR checks; and integrated physical verification capabilities.
“By continuing to work closely with Cadence, we’re ensuring that customers can use our most advanced N4P and N3E technologies and the certified Cadence digital and custom/analog flows with confidence,” said Dan Kochpatcharin, head of the Design Infrastructure Management Division at TSMC. “This joint effort combining TSMC’s technology advancements with Cadence’s leading design solutions helps our mutual customers meet the stringent power and performance requirements and quickly launch their next-generation silicon innovations to market.”
“Through our longstanding collaboration with TSMC, we’ve continued to keep our focus on creating new technologies that enable our mutual customers to achieve their PPA and productivity goals,” said Dr. Chin-Chi Teng, senior vice president and general manager in the Digital & Signoff Group at Cadence. “Our latest work with TSMC reaffirms our commitment to helping customers achieve design excellence with our flows and TSMC’s advanced technologies, and we’re always amazed by the innovations they create.”
The Cadence digital and custom/analog advanced-node solutions that have been tuned for TSMC’s N4P and N3E process technologies support the Cadence Intelligent System Design™ strategy, which enables customers to achieve system-on-chip (SoC) design excellence.
Suggested Items
Real Time with… IPC APEX EXPO 2024: Ventec Discusses New Pro-bond Family of Advanced Products
05/01/2024 | Real Time with...IPC APEX EXPOChris Hanson, Ventec's Global Head of IMS Technology, outlines the launch of four pro-bond formulas that deliver an outstanding combination of low dissipation factor (Df) with a dielectric constant (Dk) range to maximize the design window for critical PCB parameters. As Chris points out, Pro-bond is designed for low-loss, high-speed applications, while thermal-bond dissipates heat from a component through the board to a heat sink.
IPC's Vision for Empowering PCB Design Engineers
04/30/2024 | Robert Erickson, IPCAs architects of innovation, printed circuit board designers are tasked with translating increasingly complex concepts into tangible designs that power our modern world. IPC provides the necessary community, standards framework, and education to prepare these pioneers as they explore the boundaries of what’s possible, equipping engineers with the knowledge, skills, and resources required to thrive in an increasingly dynamic field.
On the Line With… Talks With Cadence Expert on SI/PI for PCB Designers
05/02/2024 | I-Connect007In “PCB 3.0: A New Design Methodology—SI/PI for PCB Designers,” subject matter expert Brad Griffin, Cadence Design Systems, discusses how an intelligent system design methodology can move some signal and power integrity decision-making into the physical design space, offering real-time feedback.
iNEMI Packaging Tech Topic Series: Role of EDA in Advanced Semiconductor Packaging
04/26/2024 | iNEMIAdvanced semiconductor packaging with heterogenous integration has made on-package integration of multiple chips a crucial part of finding alternatives to transistor scaling. Historically, EDA tools for front-end and back-end design have evolved separately; however, design complexity and the increased number of die-to-die or die-to-substrate interconnections has led to the need for EDA tools that can support integration of overall design planning, implementation, and system analysis in a single cockpit.
Cadence, TSMC Collaborate on Wide-Ranging Innovations to Transform System and Semiconductor Design
04/25/2024 | Cadence Design SystemsCadence Design Systems, Inc. and TSMC have extended their longstanding collaboration by announcing a broad range of innovative technology advancements to accelerate design, including developments ranging from 3D-IC and advanced process nodes to design IP and photonics.