Stacked Microvia Reliability: Ongoing Work and Upcoming IPC Conference

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One year ago, Happy Holden's review [1] of the 2018 IPC High-Reliability Forum reported the presentation of J.R. Strickland and Jerry Magera who described research at MSI Applied Technology into overcoming the risk of stacked microvia failures escaping standard quality assurance procedures. And their report provided a basis for the IPC white paper IPC-WP-023 [2], which addressed reliability issues associated with stacked microvias and included data collected from several other printed circuit manufacturers.

These reliability effects had been recognised for some time—field failures had been observed as long ago as 2010 in the form of temperature-related intermittent open circuits—and it was clear that a fool-proof method of quality control was urgently needed. In 2011, a test based on multiple-pass reflow with four-wire resistance measurement was adopted, which succeeded in containing the problem. And staggering the microvias became a workaround that effectively avoided the problem, although at the expense of consuming precious space in designs of increasing density.

IPC-WP-023 generated sufficient interest to justify the formation of the IPC V-TSL-MVIA Weak Interface Microvia Failures Technology Solutions Subcommittee to investigate potential causes of failures at the microvia interface and to provide a central information resource.

At this year’s IPC APEX EXPO, the V-TSL-MVIA Subcommittee held a remarkably well-attended open forum [3] to explain their objectives, discuss the issue, gather and compile data from the industry, and work on solutions to the problem by identifying root causes and implementing corrective actions. It was proposed to form teams to focus on topics, including simulation and modelling, characterisation and test methods, laminate materials, construction design elements, metallurgy, chemical processes, hole formation, and data collection.

J.R. Strickland presented a report on the current understanding of microvia weak interface failures and how they could be mitigated, concluding that best practice was to stagger microvias wherever possible and stack them no more than two high. It had been demonstrated on test panels that a microvia could be clearly observed to go open circuit during reflow and then re-establish continuity during cooling so that it would pass conventional electrical testing. And failure was not necessarily always at a specific “weak” interface.

MSI had seen examples occurring between copper fill and electroless, electroless and electrolytic, and electroless to copper pad. The MSI slides can be found and viewed in the references [4]. Happy Holden presented the early results of the industry survey. His slides can also be found and viewed in the references [5]. It was further emphasised that anyone with an interest could share their experiences with IPC by emailing Chris Jorgensen, director of technology transfer, at

In early March, IPC issued a press release The IPC Warning About Microvia Reliability for High-performance Products” published in full on I-Connect007 [6], the opening paragraph of which reads:

“The proliferation of tighter microvia densities and signal integrity requirements in printed boards within the electronics industry has revealed reliability concerns with microvia structures in high-performance products. A number of IPC OEM member companies have approached IPC with examples of microvia failures in high-profile hardware that were not observed until after bare printed board fabrication, inspection and acceptance…Many of these failures occurred within products that had already passed traditional production lot acceptance testing in accordance with existing IPC-6010 Printed Board Qualification and Performance Specifications. IPC has been provided with data showing that traditional inspection techniques utilizing thermally stressed microsections and light microscopes alone is no longer an effective quality assurance tool for detecting microvia-to-target plating failures.”

The press release also made reference to IPC-WP-023, the IPC V-TSL-MVIA Team, and the IPC APEX EXPO open forum before issuing the following warning statement, which would also be included in the forthcoming IPC-6012E, Qualification and Performance Specification for Rigid Printed Boards:

“There have been many examples of post-fabrication microvia failures over the last several years. Typically, these failures occur during reflow; however, they are often undetectable (latent) at room temperature. The further along the assembly process that the failures manifest themselves the more expensive they become. If they remain undetected until after the product is placed into service, they become a much greater cost risk and, more importantly, may pose a safety risk.”

Additionally, the press release announced that in the future, IPC would move away from traditional microsection evaluations and focus on performance-based acceptance testing.

Holden commented at length in Altium’s Industry Expert Series published on April 1 [7]. He described the new IPC thermal stress convection reflow assembly simulation test method that allowed OEMs to detect the latent microvia failures and protect themselves from possible defect escapes. IPC-TM-650, Method 2.6.27A, required the test coupon with a daisy chain composed of features used in the actual circuits to be subjected to a solder paste reflow profile to reach a peak temperature of 230°C or 260°C while connected to a four-wire resistance measuring unit for six full reflow cycles without an increase of resistance of 5%. Holden also remarked that further discussions would be undertaken at the upcoming IPC Annual High-Reliability Forum to be held in Baltimore, Maryland, May 14–16 [8]. The forum is open to IPC members and non-members, and he urged as many as possible to attend.

As a prelude to the IPC High-Reliability Forum, an informative IPC webinar on weak interface stacked microvia reliability was presented on April 17 by IPC Hall of Fame member and I-Connect007 columnist Dennis “Denny” Fritz. The complete webinar is now available on YouTube [9]. Fritz explained that product-level failure was unpredictable and historical standard test methods were not effective in detecting failures. The industry was presently in containment mode and the IPC V-TSL-MVIA Team had been formed to identify the root causes and determine appropriate corrective actions.

Fritz stressed that the webinar was not intended to scare designers and users away from microvias—they remain a very reliable PCB interconnect design tool. The webinar aimed to alert the PCB industry to a potential reliability issue associated with multiple levels of stacked microvias, although not with staggered microvia designs. The webinar further aimed to relate IPC’s methodology for determining the root causes of this phenomenon to solicit industry support in compiling data and report the industry’s best efforts to date to mitigate weak-interface microvias through recently adopted design parameters, test protocols, and product sorting.

Next, Fritz discussed the history and current understanding of the problem with reference to IPC-WP-023 and some actual microsections. He explained the fishbone diagram that had been generated to visualise and categorise all of the potential causes of the problem to compile data and eliminate items that were not contributing factors. Also, Fritz described how data mining techniques were being used for identifying patterns in large sets of test data, and reviewed methods for microvia reliability modelling and simulation.

An information survey was proposed to provide data for the IPC V-TSL-MVIA Team, and a coding system had been devised to protect the identity of individual contributors. Then, Fritz listed the specialist working teams organised to focus on the areas of simulation and modelling, characterization and test methods, laminate materials, construction design elements, metallurgy, chemical processes, hole formation and data collection, and briefly described their strategies and objectives with the longer-term goal of providing guidance on design, material selection, and processing to achieve reliable higher density structures.


  1. Holden, H. "The IPC High-reliability Forum for Mil-aero and Automotive Sectors," PCB007 Magazine, August 2018
  2. "IPC-WP-023: IPC Technology Solutions White Paper on Performance-based Printed Board OEM Acceptance, Via Chain Continuity Reflow Test—The Hidden Reliability Threat."
  3. Jorgensen, C. "Microvia Subcommittee Brings Industry Together, Hosts Open Forum."
  4. Strickland, J.R., & Magera, J. “Microvia Weak Interface Failures: Current Understanding and Mitigation.”
  5. IPC TSL Microvia Team, Holden, H., Carter, M., & Baccam, J. “Data Collection Process for the Weak Microvia Interface Problem.”
  6. IPC. “IPC Issues Warning on Microvia Reliability for High-performance Products,” March 7, 2019.
  7. Holden, H. “The IPC Warning About Microvia Reliability for High-performance Products,” April 1, 2019.
  8. Register: IPC High Reliability Forum and Microvia Summit.
  9. IPC Webinar: IPC High-Reliability Forum and Microvia Summit.


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