High-Performance IC Substrate Manufacturing at an Inflection Point

Reading time ( words)

Driven by advanced packaging substrate needs, the industry has reached an inflection point in IC substrate manufacturing. Increasing I/O counts are driving substrate layer counts to more than 20. Larger die sizes and multiple die mounted on the substrate are driving the need for larger body sizes, up to 100 mm x 100 mm. 

Some companies use a silicon interposer with multiple redistribution layers (RDLs) to provide the connection between logic and high bandwidth memory (HBM). Others use fan-out on substrate with RDLs. A number of companies are considering new RDL on organic solutions with 2µm line width and spaces and Intel is exploring an expanded role for its Embedded Multi-die Interconnect Bridge (EMIB).

Several companies are making investments in fab-like processing equipment for the next generation IC packaging substrates. These developments are described and a forecast for high-density substrates is provided in TechSearch International’s newest Advanced Packaging Update.

TechSearch International’s annual survey on substrate design rules is highlighted, with special coverage of suppliers of laminate flip chip BGA and CSP substrates worldwide. The design rules include body size, core thickness, via and pad diameter, minimum bump pitch supported, and substrate finish.

The latest Advanced Packaging Update is an 85-page report with full references and an accompanying set of 42 PowerPoint slides.

About TechSearch International, Inc.

TechSearch International, Inc., founded in 1987, is a market research leader specializing in technology trends in microelectronics packaging and assembly. Multi- and single-client services encompass technology licensing, strategic planning, and market and technology analysis. TechSearch International professionals have an extensive network of more than 18,000 contacts in North America, Asia, and Europe.



Suggested Items

The Advantages of Non-sludge Acid Copper Products

09/04/2019 | Barry Matties, I-Connect007
Mike Wood, technical director with Cerambus Asia Pacific, discusses the acid copper product from Cerambus Technology Inc. that doesn't generate sludge during the plating process and operates at higher production output by using higher current density. He talks about why this is important for the state of the vertical continuous plating (VCP) market in Asia, and the trends he’s seeing in that space.

The State of Plating

09/03/2019 | Marc Ladle, Viking Test Ltd.
Increasingly, PCB design technology utilises buried and blind via holes and plated via fill is also becoming more and more common. The buried and blind holes mean that the loading on the plating equipment is multiplied by the number of different inner layer connections. The same technology means that equipment needs to deal with thinner and thinner materials.

Innovative Electroplating Processes for IC Substrates

08/27/2019 | S. Dharmarathna, S. Maddux, C. Benjamin, I. Li, W. Bowerman, K. Feng, and J. Watkowski, MacDermid Alpha Electronics Solutions
The decreasing chip scales and smaller line/spacing distances have created unique challenges for both the PCB industry and the semiconductor industry. This paper discusses innovative additive packages for direct-current copper electroplating specifically for IC substrates, which offer better trace profile and deliver via fill and through-hole plating. It also describes two electrolytic copper plating processes, the selection of which could be based on the via size and the dimple requirements of the application.

Copyright © 2019 I-Connect007. All rights reserved.