Real Time with… Altium Live Europe 2020: Rick Hartley’s Secrets of PCB Optimization
As Lawrence Romine said in his introduction, “There’s that moment when you sit in the crowd and hear Mr. Rick Hartley speak that you know you’ve arrived in PCB design.” With 50 years in the industry focused on circuit and PCB design—and as a specialist in EMI, noise, and signal integrity issues—Rick Hartley was invited to talk about PCB optimisation. But meaning what? There were a lot of things that could be optimised on a PCB.
In this particular case, Hartley was going to talk about designing boards to optimise manufacturability, with particular regard to cost-effective fabrication. I was eager to hear what he had to say, particularly having been for many years a fabricator myself, with much of my time spent talking to designers. The ones I liked best asked all the what-if questions before they began a new design. The ones who caused the most annoyance belonged to the “over-the-wall” category. It gave me enormous satisfaction to arrange for them to visit our factory then surprise them with an invitation to help manufacture what they had designed. They would say, “I never knew it was that complicated.”
Hartley made it clear that although he could easily make a really long presentation on the subject—eight hours at least—he would cover as much as he could in his conference time slot. His overarching message, which he repeated many times, was “Talk to the fabricator,” commenting, “Fabricators know their processes and know them well. If we ship them designs that make sense, that are well-thought-out, they won’t have scrap. When they have high levels of scrap, it’s because we as designers have not done our job right.” The question to ponder was, “When there’s scrap at a fab house, who do you think pays?”
He discussed some of the key items of information that a fabricator would check once a design was received for manufacture, the first of which was board size in the context of economic material utilisation. Next came the material choice, number of layers, and layers per given board thickness. There was still a common presumption that all circuit boards must be one-sixteenth of an inch (62 mils) thick, like the early single and double-sided designs and the card-guides they fitted into. He urged designers to think carefully about the consequences when nominating board thickness, commenting on the difficulty in manufacturing a 16-layer controlled impedance design to a finished thickness of 62 mils.
He recalled an early experience of working with a fabricator to optimise the finished thickness of a series of 12-layer designs, taking into account the issues of performance, ease-of-manufacture, and cost-effectiveness, arriving at a figure of 75 ±5 mils. Drilling cost obviously increased with the number of holes, but probably more significant factors were minimum hole size and aspect ratio, pad-to-hole size ratio, and power and ground plane clearance from the hole wall. IPC standards were a useful reference for clearances and tolerances.
Continuing down his list of critical parameters, he discussed minimum conductor widths and spaces, particularly in relation to copper foil thickness and copper balance layer-to-layer. Explaining at each stage the reasons for preferred and non-preferred options, he covered the topics of solder masks and component legends, final finishes, and metallisations, as well as edge connectors, controlled impedance, and design-specific features.
For guidance on actual fabrication cost, he referred to the “fabrication report card” described by Happy Holden, where each line-item was associated with a weighting factor, and low numbers were to be preferred when establishing cost per panel. Mention of cost per panel led to a discussion on preferred panel sizes and material utilisation, reminding designers that the panel also had to accommodate test coupons, tooling holes and copper-thieving in the perimeter, and room for profile-machining between individual circuits.
Again, the advice was, “Talk to the fabricators and make sure your design fits their panels and their processes.” Not forgetting the assembler, Hartley reminded designers to be aware of the keep-out areas necessary for supporting and transporting the board through the assembly process and not to fill them with components. Alternatively, put multiple small boards into a sub-panel. “Talk to the assembler as well.”
Hartley gave a brief introduction to the circuit board manufacturing process, taking a basic four-layer multilayer as an example, and proceeding step by step through all of the principal stages, with his explanations aided by clear graphics. He made a particular point about non-uniform plating distribution on outer layers with unbalanced copper but advised against allowing the fabricator to fill spaces with thieving copper to even-out the plating because of potential induction effects. The designer would need to make modifications with manufacturability in mind whilst maintaining the signal integrity of the design. A copper pour, attached to ground or power, could help but might not be the answer.
On the subject of etch-compensation, he advised designing at nominal conductor width and leaving it to the fabricator to calculate the appropriate etch-factors. “Don’t compensate for the fabricator’s needs. Make sure you design so they can produce your board. Know what they can and can’t produce, and design around their needs, then send them the design and leave them alone.”
There were many more details to understand—he could easily have filled the other seven hours he mentioned—and many more questions to ask the fabricator: “Don’t assume. Talk to the fabricator, ask the questions, get to know the most knowledgeable person at every fab shop your company uses—someone who understands.”
Listening to Rick Hartley was like a breath of fresh air. And his one-hour (and a bit) session provided a wealth of advice on how to accomplish the goal of optimising designs for cost-effective, high-quality manufacturing.