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Nolan Johnson speaks to Greg Link of WUS Printed Circuit Co. to gain a better understanding of where DFM fits in from a fabricator’s perspective.
Nolan Johnson: Greg, what we call DFM in the PCB world, the semiconductor community calls layout verification. The PCB industry refers to the software tools as DFM, and yet, I would posit that the software tools don’t actually perform a DFM.
Greg Link: I agree.
Johnson: From a fabricator’s point of view, where is the mismatch between what design for manufacturing (DFM) should be and what the tools do in the market?
Link: DFM should be, by definition, designing to improve manufacturability, but most of the time, we fix an error here or an error there. The tool is not guiding us by saying that this is what we want to do to improve how a board is made, this is how expensive it is to make, or how quick it is to make. Is this really what the customer needs? Those types of questions aren’t really being asked. And I don’t know how you do that in a functional world. I think this is the weakness.
Johnson: You’re right. Philosophically, the goal is to give guidance that increases yields, simplifies the manufacturing steps, and maximizes your mean time between failure. If your goal is using design rule checks to make sure your trace and space parameters are sufficient, then that’s a piece of it, but that doesn’t get you to your goal.
Link: Right. It needs to be a separate tool that our end-customers need to run through. For example, I was just looking at a board that had four-mil line and spaces with PFE inside of a pitch; there were four lines together, and then suddenly there were two more lines that were spaced, six mils apart. You look at and say, “If six mils is okay here, and here, why is four mils needed there?” There’s really no reason for it when you talk to the customer and tell them, “If you look at this area, this four-mil pitch makes it feel really hard to do, so could you just space all these out?” But by that time, they’ve already done all their engineering to prove out that this is going to work like they want it, not like it’s manufactured to be made, but like they want it to do. With that extra cost that they have to apply, they may say, “We’ve already done the modeling, and everything seems to be fine. If you can make it this way, please make it this way. If you can’t, then we need to have other discussions.”
Johnson: That is part of the mismatch, right? In my opinion, the DFM tools should be called CFM, or “check for manufacturing,” because you’ve already done the design. The design has to be complete to start the determination whether it’s designed to be manufacturable.
In your experiences working with DFM tools, can you draw a correlation between passing the DFM analysis using the rule deck, and having increased manufacturability yields?
Link: Oh, absolutely. You can draw a correlation without a doubt.
Johnson: It does help, but it involves a great deal of human heuristic knowledge to make it work.
Link: Right. And sometimes at the expense of annoying the customers because you’re asking them questions that they didn’t really want to be asked. They want you to simply analyze their board and see if there are any glaring problems; they don’t want to be second-guessed on their design. It takes the PCB manufacturers out of that uncomfortable situation that says, “Hey, what if you did this and that?” We don’t want to be designing boards, we want to be building them. Sometimes those conversations can be pretty tricky to have.
Johnson: It seems in some cases, the engineers, and I’m probably being unfair, but they don’t want to be bothered with those details on the manufacturing side. I’ve heard it said, “I’ve done my design, here you go, just make it happen; make my vision work.” And yet you have to talk about these messy little details like situational areas of trace and space or the like. The CAM department at a fabricator brings up these details to increase their customers’ yields, or to decrease the customer’s manufacturing costs.
Johnson: What are some of the most common DFM errors that your team sees? You know that these are going to show up, so you’re looking for them immediately.
Link: Let’s talk about checks that we catch. The netlist doesn’t match up, hole counts are off, the dimensions are wrong from a fab print to a Gerber file. Those are probably the major ones. From a design, checks we catch might be gaps in reference ground plane. It could be line spaces, like I just mentioned, where there’s an inconsistency between how much space you have in area A vs. area B. It would be designing outside of what would be normal manufacturing. For example, they’re asking for 1.5 mils of copper, and I have a 6-mil drill hole. You just don’t have enough room to get copper through that area. Those would be common design for manufacturability things we might see.
Johnson: WUS does some complex work. Can you characterize that for me? What’s the WUS sweet spot?
Link: We have four different facilities, and each one has its own sweet spot, which is the way it should be. Our automotive plant is going to be six- or eight-layer board, with HDI/hybrid, possibly RF materials. They’re usually smaller platforms. The Taiwan facility is a high degree of HDI, usually smaller platforms as well, and generally not the ultra-low loss materials— more like Megtron 6 or equivalent, and higher loss materials
The C3 facility is our most advanced facility, and the sweet spot would be 24-32 layers, HDI, backdrill. That generally makes six or greater materials. The C4 facility sweet spot is 10- to 12-layer board range of different materials with panel sizes that don’t go past a 21x24 working panel size.
Johnson: That’s four different facilities, four different sweet spots and setups, and four different rule decks, if you will. You must characterize each of your facilities uniquely within the design for manufacturability tool environment.
Link: Right. For most customers, we either only use one facility, or we know well in advance which facility it’s going to go through. So, customer N might say, “Here’s a 14-layer PCIE card,” and we already know that’s going to go into the C4 facility. If they talk about a 26-layer, HDI build, it’s going to go in the C3 facility.
Johnson: Okay, so how do you assist your customers in doing that? Or are they even interested?
Link: They definitely are. With customers like that, we have periodic meetings with them to talk about details so it doesn’t come up as a surprise. We are able to keep them aware of the types of technology available in the facilities. We do pretty good work from front-end engineering, working with the customer before boards are designed to completely be able to talk through issues that will eventually show up. We try to get them before it starts, basically.
Johnson: This can be time-intensive.
Link: It can be, yes.
Johnson: You’re still working on a very manual process here for putting that information together. For example, there is no use of AI at this point to help with the process of thinking through manufacturability decisions?
Link: That’s correct, and we want it that way. We give our customers a set of rules that say, “These are the rules that we want to be bound by,” and then our competitor comes up with a different set of rules. Now maybe they’re okay with 94% yield, and we were targeting a 95% yield. Suddenly, their rules look better than ours because they’re willing to accept a little bit more loss in yield, or more risk to reliability. Because all suppliers don’t have the same standards, they’re gauged against it on paper: “Can WUS do this? Can XYZ do that? Oh, XYZ can do it, but WUS can’t. Okay, we’ll give them the work.”
To read this entire interview, which appeared in the July 2021 issue of PCB007 Magazine, click here.