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Phase 2 of the 1st Level Interconnect Void Characterization project focused on understanding the potentially adverse impact that voids in first level interconnect materials have on the reliability of the electrical interconnect. The formation of small voids can occur in solder-based flip chip joints during the assembly process. This can be a concern for applications that involve high electrical and thermal flux across flip chip packages because the presence of a void can accelerate complete open failure due to electromigration.
The project team conducted experiments to understand the relationship between voids and joint reliability (electrical and mechanical) and worked on recommendations for acceptable voiding characteristics for flip chip interconnects. This end-of-project webinar will present the reliability test results for first level interconnection — performed by electromigration, temperature cycle and thermal shock testing — and will include descriptions of the test packages, reliability test conditions, test data of cross-section images and EBSD data.
Registration
This webinar is open to industry; advance registration is required, check iNEMI's website. Two webinars with the same content are scheduled — please join whichever one fits your schedule.
Session 1 (APAC)
Thursday, June 16, 2022
10:00-11:00 a.m. JST (Japan)
9:00-10:00 p.m. EDT on June 15 (Americas)
Session 2 (Americas & Europe)
Thursday, June 16, 2022
9:00-10:00 a.m. EDT (Americas)
3:00-4:00 p.m. CEST (Europe)
10:00-11:00 p.m. JST (Japan)
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