Happy’s Design Tips for Material Conservation


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Note: For this issue, Happy Holden provided a range of options for designers who are seeking to conserve materials in their next design. He also offered an example of the relative cost index, or RCI, that he developed at HP exclusively for PCB design. With this RCI, designers can figure out the relative cost of a new design compared to an eight-layer through-hole board.

  • Consider making the board thinner; eliminate prepregs
  • Design to HDI for smaller board or fewer layers (Figure 1 and Reference 1)
  • Design inner layers with 1 to 2 mil smaller traces/spaces
  • Swing vias for BGA breakout can reduce layer count 
  • Nesting and rotation on panels
  • Using HDI “skip vias” to eliminate a build-up layer

Consider using new technologies:

  • VeCS can reduce layer count (Figure 2 and Reference 2)
  • Additive creates more routing per layer and smaller boards
  • Switch HDI layers to RCF (RCC)
  • Power mesh can yield fewer layers (Reference 3)
  • Landless vias on the surface can mean higher routings (Figure 3 and Reference 4)
  • Smaller panel peripheral border
  • Different panel sizes for higher utilization
  • Add-on 0.062" gold fingers as components
  • Board replacement for X-outs and repanelization (Reference 5)
  • Inkjet solder mask just on traces/pads
Happy_Tips_Figure1.jpg

Figure 1: Replacement chart for through-hole to HDI with Relative Cost Index. Note: RCI = the relative cost compared to an eight-layer through-hole board (RCI=1.0). DEN = total wiring in inches per square inch (diagonals of equivalent density).

Happy_Tips_Figure2.jpg

Figure 2: VeCS (Vertical Conductive Structures) is a licensed technology using low-footprint vertical controlled impedance interconnect with low-leakage ground shielding capable of matching interconnect impedance with SE and differential microstrip and striplines. VeCS also provides high-density differential routing solutions in =/< 1.0 mm BGA area. Unique “anti-pad” layers provide a higher cross-section area for power and heat dissipation.

Happy_Tips_Figure3.jpg

Figure 3: A variety of examples of landless vias on the outer layers of a PCB. 

References

  1. The HDI Handbook, by Happy Holden, et al, BR Publishing, Salem, Oregon, 2009.
  2. Happy’s TechTalk #1: Vertical Conductive Structures (VeCS), by Happy Holden, PCB007 Magazine, October 2021.
  3. Innovative Use of Vias for Density Improvements,” by Happy Holden, The PCB Magazine, November 2016.
  4. Against the Density Wall: Landless Vias Might be the Answer, by Happy Holden, The PCB Magazine, June 2016.
  5. Happy’s TechTalk #6: Looking at the Process of Repanelization, by Happy Holden, PCB007 Magazine, March 2022.

This article originally appeared in the August issue of Design007 Magazine, here.

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