# Shrinking Silicon, Growing Signal Integrity Challenges

What happens when die sizes shrink? As IPC design instructor Kris Moyer explains, quite a bit. Shrinking silicon can mean rising signal speed and rise times, and traditional PCB designers may find themselves dealing with problems formerly only seen by RF engineers.

We asked Kris to discuss the pros and cons of silicon shrinkage and some of the techniques and trade-offs that PCB designers and design engineers need to understand as they find themselves entering the RF arena.

Andy Shaughnessy: This issue focuses on the effects of shrinking silicon on a board’s signal integrity and EMI. So, what do PCB designers need to understand about die shrinkage?

Kris Moyer: Basically, the main thing that happens when you shrink the size of the die is that it shrinks the length of the channel of the transistors inside the die. What that effectively does is it increases the speed of the circuit, meaning it decreases the rise time or the fall time. Then you end up having to start treating your traces, geometries, and transmission lines almost as if they're RF designs.

We've heard for decades that RF designs are their own special little area of black magic, because we start dealing with all these waves and fields and so on. We say in digital design that it's the rise time and not the frequency. Which is the driving force, the key factor, that causes the need for all these high-speed designs? What is the frequency content?

Fourier's theorem says any wave form—square wave, triangle wave, sawtooth wave, or any wave form—can be recreated as a superposition of a sufficient amount of sine waves and cosine waves of sufficiently higher harmonics. Let’s take a fundamental frequency, 1 kilohertz. And you have A1, A3, A5 and A10 kilohertz. You have all these harmonics, we superimpose them, and you end up getting a square wave. Well, how square does that square wave need to be? This is the part that throws a lot of designers off.

When we talk about rise time, we're really talking about the time it takes that square wave, the digital signal, to change from a logic 0 to a logic 1. As the die shrinks, that time also shrinks. About 20 years ago, we were having rise times and fall times in the multiples of nanoseconds—five to 10 nanoseconds. It took that signal five to 10 nanoseconds to change from a logic 0 to a logic 1. I was just looking at one FPGA with rise times as fast as 0.25 nanosecond, and that's at 16 nanometers.

My friends who work in next-generation silicon at some of the big telecom companies are working in 5, 3, and 2 nanometer, and going sub 100 picosecond. Instead of 0.25 nanosecond, it’s 0.1 nanosecond and 0.05 nanosecond rise times. They’re such incredibly fast rise times that the number of harmonics we need to create a vertical square edge that transitions from A0 to A1 that fast means that the frequencies involved in that superposition in that Fourier series are up into the multiple gigahertz of frequency content. That means that you're in the RF frequency range.

To read this entire conversation, which appeared in the February 2023 issue of Design007 Magazine, click here.

## Tips and Tricks in Today’s Designs

03/23/2023 | Kelly Dack, CID+
Filbert Arzola of Raytheon Intelligence & Space taught a Professional Development course at IPC APEX EXPO on general design practices. During a break, Filbert spoke with Kelly Dack about some of today’s design strategies and how designers are reacting to them. What matters most?

## True Experts Can Cite Their Sources

03/23/2023 | I-Connect007 Editorial Team
We’ve heard a lot lately about the need to identify tribal knowledge within our organizations. How do you know whether an “expert” is sharing documented knowledge or it’s just something they learned at their first job during the Carter administration? We asked IPC design instructor Kris Moyer to explain his process for separating the wheat from the chaff, so to speak, in design knowledge. As he points out, a true expert will not be afraid to cite the sources and data sets behind their arguments.

## Runner-up Discusses IPC Design Competition

03/16/2023 | I-Connect007 Editorial Team
PCB designer Adam Thorvaldson of Innovex was a finalist in this year’s IPC Design Competition at IPC APEX EXPO. He came in second place in this final heat, which is quite a feat, considering that the contest started last fall with 49 contestants from around the globe. We asked Adam to share his thoughts on the competition, what it means to be one of the winners, and any ideas about improving the contest for 2024 in Anaheim.