Developing Advanced Substrates for Die Packaging and Test

Reading time ( words)

Semiconductor wafer-testing interface PCBs require a fine-pitch interposer/substrate to transfer a larger pitch (greater than 0.4 mm) to a fine pitch (less than 150 mm). The interposer, which serves as the electromechanical interface between the tester and the wafer requires fine pitch, high pin count, high I/O density, and vertical compliance.

Interposers are thus becoming a critical component for the testing interface. However, these boards are typically only available from a few high-end substrate manufacturers located in Asia. The associated longer lead times and single-source suppliers have made acquiring these boards a potential time-to-market showstopper for semiconductor manufacturers in need of them.

In early 2017, R&D Altanova (RDA) saw an opportunity in this space and began developing substrate technology to meet this need (Figure 1). In the beginning, we faced numerous challenges in identifying equipment, raw materials (e.g., dielectrics, process chemicals, and others), process know-how, and other requirements to accommodate low-volume, high-end applications.


Figure 1: This substrate for wafer probing is one example of the innovations developed by R&D Altanova to meet evolving manufacturing requirements.  

Meeting the Need

Following a methodical approach, we used design of experiments (DOE) techniques to test different processes and materials on a small lab bench scale environment to check process yields, repeatability, reliability. This enabled us to slowly migrate to a low-volume semi-automatic production process for developing these new substrates.

Toward the end of 2017, we delivered the first 1-2-1 substrate 90 mm-pitch board with 10 mm lines and 15 mm spaces. Since then, we have continued to upgrade tools and develop processes to support high-end substrates.Today, we can build 12-2-12 or 12-n-12 (n-multilayer center core 24 layers), with 10 mm lines, 15 mm spaces for 100 mm x 100 mm boards.


Figure 2: This table lists the substrates R&D Altanova designed and manufactured between July and October 2022.  

In 2022, we completed 50 new substrate designs and 3,500 PCBs of varying complexity (from 2-2-2 to 12-24-12) and board sizes (from 12 x 12 mm to 100 x 100 mm). Figure 2 lists the substrates we designed and manufactured between July and October 2022. Our primary focus was to build substrates for wafer testing, but supply-chain disruptions due to the COVID-19 pandemic opened a new market opportunity—creating substrates for die packaging. Figure 3 depicts a substrate cross-section, illustrating the low coefficient of thermal expansion (CTE) enabled by our approach, as well coplanarity and other specifics.


Figure 3: This example cross-section of substrate, post-thermal stress, illustrates the low CTE coplanarity and other beneficial parameters enabled by R&D Altanova’s development approach.  

Looking Toward the Future

Even with supply-chain disruptions easing, we continue to add new customers to support the initial development work. This is due in large part to our ability to meet short delivery lead times of four to eight weeks, depending on project complexity.

We are excited to have expanded our offerings through the development of these innovative new substrates. As the demand for this technology continues to grow, we will continue to develop new substrates to meet customers’ requirements. Figure 4 shows our high-volume manufacturing (HVM) capabilities for redistribution layer (RDL) metal lift-off (MLO).


Figure 4: This table shows the manufacturing capabilities that R&D Altanova provides.  


This development work was made possible thanks to the foresight of James Vincent Russell (R&D Circuits founder), the efforts of our stellar team of engineers, and the unflagging support of our president and CEO Seyed Paransun. 

Dan Turpuseema is director of Substrate Technology, R&D Altanova (a subsidiary of Advantest America).



Suggested Items

IPC APEX EXPO 2023 Special Session: Advanced Packaging

03/13/2023 | Pete Starkey, I-Connect007
The IPC APEX EXPO Special Session on Advanced Packaging this year attracted enormous interest, with Conference Room 2 at capacity long before the session began. Even with lots of extra seats squeezed around the edges, the session was standing room only for the just-in-time arrivals. IPC Chief Technology Officer Matt Kelly opened proceedings by introducing a distinguished panel of experts: Jan Vardaman, president and founder of TechSearch International; Sam Salama, CEO of Hyperion Technology; Matt Neely, director of process engineering at TTM Technologies; and Jim Fuller, VP of engineering technology at Sanmina.

Understanding the UHDI Market

11/28/2022 | I-Connect007 Editorial Team
The more we investigate UHDI in the current market, the more advanced packaging becomes a part of the conversation. Yet there are so many questions to be answered. The I-Connect007 Editorial Team met with Calumet’s Todd Brassard and Meredith LaBeau recently to get answers to these questions and find out where the UHDI market is headed.

IPC Symposium: U.S. Must Address Critical Gaps in Advanced Packaging Needs

10/12/2022 | Nolan Johnson, I-Connect007
There is a significant capability gap in advanced substrate packaging in North America, forcing all semiconductors to be packaged in Asia and leaving North America at risk in its supply chain. This was a common theme during a two-day IPC Advanced Packaging Symposium, which launched yesterday at the Kimpton Monaco hotel in Washington, D.C.

Copyright © 2023 I-Connect007 | IPC Publishing Group Inc. All rights reserved.