-
- News
- Books
Featured Books
- pcb007 Magazine
Latest Issues
Current IssueThe Growing Industry
In this issue of PCB007 Magazine, we talk with leading economic experts, advocacy specialists in Washington, D.C., and PCB company leadership to get a well-rounded picture of what’s happening in the industry today. Don’t miss it.
The Sustainability Issue
Sustainability is one of the most widely used terms in business today, especially for electronics and manufacturing but what does it mean to you? We explore the environmental, business, and economic impacts.
The Fabricator’s Guide to IPC APEX EXPO
This issue previews many of the important events taking place at this year's show and highlights some changes and opportunities. So, buckle up. We are counting down to IPC APEX EXPO 2024.
- Articles
- Columns
Search Console
- Links
- Events
||| MENU - pcb007 Magazine
Developing Advanced Substrates for Die Packaging and Test
April 20, 2023 | Dan Turpuseema, AltanovaEstimated reading time: 2 minutes
Semiconductor wafer-testing interface PCBs require a fine-pitch interposer/substrate to transfer a larger pitch (greater than 0.4 mm) to a fine pitch (less than 150 mm). The interposer, which serves as the electromechanical interface between the tester and the wafer requires fine pitch, high pin count, high I/O density, and vertical compliance.
Interposers are thus becoming a critical component for the testing interface. However, these boards are typically only available from a few high-end substrate manufacturers located in Asia. The associated longer lead times and single-source suppliers have made acquiring these boards a potential time-to-market showstopper for semiconductor manufacturers in need of them.
In early 2017, R&D Altanova (RDA) saw an opportunity in this space and began developing substrate technology to meet this need (Figure 1). In the beginning, we faced numerous challenges in identifying equipment, raw materials (e.g., dielectrics, process chemicals, and others), process know-how, and other requirements to accommodate low-volume, high-end applications.
Figure 1: This substrate for wafer probing is one example of the innovations developed by R&D Altanova to meet evolving manufacturing requirements.
Meeting the Need
Following a methodical approach, we used design of experiments (DOE) techniques to test different processes and materials on a small lab bench scale environment to check process yields, repeatability, reliability. This enabled us to slowly migrate to a low-volume semi-automatic production process for developing these new substrates.
Toward the end of 2017, we delivered the first 1-2-1 substrate 90 mm-pitch board with 10 mm lines and 15 mm spaces. Since then, we have continued to upgrade tools and develop processes to support high-end substrates.Today, we can build 12-2-12 or 12-n-12 (n-multilayer center core 24 layers), with 10 mm lines, 15 mm spaces for 100 mm x 100 mm boards.
Figure 2: This table lists the substrates R&D Altanova designed and manufactured between July and October 2022.
In 2022, we completed 50 new substrate designs and 3,500 PCBs of varying complexity (from 2-2-2 to 12-24-12) and board sizes (from 12 x 12 mm to 100 x 100 mm). Figure 2 lists the substrates we designed and manufactured between July and October 2022. Our primary focus was to build substrates for wafer testing, but supply-chain disruptions due to the COVID-19 pandemic opened a new market opportunity—creating substrates for die packaging. Figure 3 depicts a substrate cross-section, illustrating the low coefficient of thermal expansion (CTE) enabled by our approach, as well coplanarity and other specifics.
Figure 3: This example cross-section of substrate, post-thermal stress, illustrates the low CTE coplanarity and other beneficial parameters enabled by R&D Altanova’s development approach.
Looking Toward the Future
Even with supply-chain disruptions easing, we continue to add new customers to support the initial development work. This is due in large part to our ability to meet short delivery lead times of four to eight weeks, depending on project complexity.
We are excited to have expanded our offerings through the development of these innovative new substrates. As the demand for this technology continues to grow, we will continue to develop new substrates to meet customers’ requirements. Figure 4 shows our high-volume manufacturing (HVM) capabilities for redistribution layer (RDL) metal lift-off (MLO).
Figure 4: This table shows the manufacturing capabilities that R&D Altanova provides.
Acknowledgments
This development work was made possible thanks to the foresight of James Vincent Russell (R&D Circuits founder), the efforts of our stellar team of engineers, and the unflagging support of our president and CEO Seyed Paransun.
Dan Turpuseema is director of Substrate Technology, R&D Altanova (a subsidiary of Advantest America).
Suggested Items
Intel Brings AI-Platform Innovation to Life at the Olympic Games
04/18/2024 | BUSINESS WIREIntel announced its plans for the Olympic and Paralympic Games Paris 2024. Bringing AI Everywhere, Intel will implement artificial intelligence technology powered by Intel processors on the world’s biggest stage.
The Connection Between Wire Harness and Box Build
04/17/2024 | Nolan Johnson, I-Connect007Christina Rutherford is a technical lead and expert in materials engineering at Honeywell, where her specialty is the design, specification, and manufacture of cables and wire harnesses. Rutherford also sits on the committee for IPC/WHMA-A-620. In this conversation, we explore the changing dynamics in wire harnesses and how they relate to box build. Christina’s standards work allows her to draw insightful parallels between wire harness and box build.
Real Time with... IPC APEX EXPO 2024: Innovations in Thermal, Warpage, and Strain Metrology
04/17/2024 | Real Time with...IPC APEX EXPOEditor Nolan Johnson talks with Neil Hubble, president of Akrometrix, about the company's leadership in thermal, warpage, and strain metrology. Neil details how Akrometrix is committed to addressing customer challenges through technological evolution, innovative solutions, and a focus on data processing. A tabletop unit for thermal warpage testing is showcased at IPC APEX EXPO this year.
Hentec/RPS Publishes an Essential Guide to Selective Soldering Processing Tech Paper
04/17/2024 | Hentec Industries/RPS AutomationHentec Industries/RPS Automation, a leading manufacturer of selective soldering, lead tinning and solderability test equipment, announces that it has published a technical paper describing the critical process parameters that need to be optimized to ensure optimal results and guarantee the utmost in end-product quality.
Connect the Dots: Designing for Reality: Prioritizing Manufacturability
04/11/2024 | Matt Stevenson -- Column: Connect the DotsRealistic PCB designs should prioritize manufacturability and reliability of the PCB as well as meet the other design requirements. To do so, one must account for the production variables associated with individual manufacturing partners. Understanding and creating robust PCB designs, especially in terms of board manufacturing, requires a lot of attention to detail. When more detail is included in the design, the manufacturing process goes more smoothly, and process yields are higher.