Case Study: Utilization of Buried Capacitance

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Embedding capacitive layers inside the PCB can reduce the number of chip decoupling capacitors on the PCB surface, while greatly improving the performance of the power distribution system. This technical paper, presented at DesignCon 2008, compares the performance of a standard PCB design to one using various types of buried capacitance layers with a reduced number of SMT decoupling capacitors.

The paper was authored by Jun Fan, University of Missouri-Rolla; Norm Smith and Jim Knighten, Teradata: John Andresakis, Oak-Mitsui Technologies; Yoshi Fukawa, TechDream; and Mark Harvey, Sanmina-SCI.

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