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HDI Book Chapter 1: Introduction to High-Density Interconnects
January 15, 2009 |Estimated reading time: 33 minutes
The Evolution of Electronics
Electronics is a relatively new industry, only about 60 years old now. From its beginning in WWII, with communications, radar, and ammunition fusing (especially the radar-altimeter electronic fusing for the fi rst atom bomb), electronics has evolved into the world's largest industry. All electronic components must be interconnected and assembled to form a functioning unit. The design and manufacture of these interconnections have evolved into a separate discipline called electronic packaging. Since the early 1940s, the basic building block of electronic packaging has been the printed wiring board (PWB). This book outlines the advanced design approaches and manufacturing processes needed to produce the most complex of these PWBs, the high-density interconnects (HDI).
This chapter introduces the basic considerations, main advantages, and potential obstacles that must be accounted for in the selection of high-density interconnection methods for electronic systems. Its main emphasis is on the analysis of wiring and component density and the potential effects that the selection of various HDI board types and design alternatives could have on the cost and performance of the complete electronic assembly.
FIGURE 1: Electronics have evolved in density from the 1940s, when first used, to the current state of high-density interconnects that include 3D stacking and embedded components. (Source: Joe Fjelstad, Silicon Pipe)
The continuing increase in component performance and lead density, along with the reduction in package sizes, have required that PWB technology fi nd corresponding ways to increase the interconnection density of the substrate. With the introduction and continued refi nement of such packaging techniques as the ball grid array (BGA), chip-scale packaging (CSP), chip-on-board (COB), and system-in-package (SiP), traditional PWB technology has approached a point where alternative ways of providing high-density interconnection have had to be developed. This book will defi ne HDI in detail and provide insights into the design, electrical performance, materials, fabrication processes, inspection/ testing, and assembly of these complex structures, as illustrated in Figure 1.
Interconnect Trends
The interconnect trends discussed in this book will be those at the high end of PWB technology-the HDI or buildup multilayers (BUM) which are driven by silicon technology. The impact of the semiconductor trend is in the forms of electronics packaging and interconnect technologies. This effect directly infl uences IC packaging via die interconnect and PWB HDI technologies.
Electronic Packaging and Interconnection
The technology migration to support higher electronic packaging and interconnection is made up of integrated circuit (IC) packages and printed wiring boards.
Integrated Circuit Packages
IC packages have four major forms:
- Peripheral leaded packages
- Plastic and ceramic ball grid array packages
- Flip-chip BGA packages
- Wire bond and fl ip-chip chip-scale packages
Printed Wiring Boards
PWBs have four main forms:
- Single- and double-sided
- Multilayer
- Flexible circuits
- Build-up multilayers
IC Technology Trends
Integrated circuit technology has been the driving force in electronics since the early '60s. The trends in IC technology are:
- Shrinking gate size - down to the current 45 nm
- Die size reduction - the opportunity for "die shrink"
- Voltage reduction - the need to control power dissipation
- Higher gate integration - currently, over 1 billion transistors can be on a die
- Faster signal rise times - higher frequencies and clock rates
As seen in Figure 2, these trends lead to other effects in packaging and PWBs, most notably, more complex BGAs.
- Faster rise times -> Smaller packages -> Finer pitch
- Higher gate integration -> Higher I/O -> Finer pitch
- Higher gate integration -> Higher current -> More PWR/GND pins -> Finer pitch
- Faster signal rise times & lower voltages -> Narrowing noise margins -> Smaller packages -> Finer pitch
- Faster rise times -> Sensitivity to Inductance and Capacitance -> Thinner packages -> Lower Dk ->
Shorter signal paths -> Smaller packages
- Lower Costs -> Smaller Packages
- Sensitivity to Inductance & Capacitance -> Elimination of pins and balls -> Fine-pitch LGAs
- Faster signal rise times -> More GND pins -> More I/Os -> Finer pitch
- Higher I/O & Finer pitch -> Area array packages
Integrated Circuit Packages
Integrated circuit packaging, system-in-package and multi-chip modules will be covered in more detail in Chapter 16 of this book. As a result of the technology trends in IC technology, IC packaging has moved from low-count peripheral leadframe to more complex area-array packages of higher I/Os and fi ner-pitch. This change can be seen in Figure 3.
The IC chip feature sizes and bonding pads have been constantly reduced in size, as shown in Figure 4. The resulting packages are 1.0 mm pitch, 0.8 mm pitch, 0.65 mm pitch and even 0.4 and 0.5 mm pitches. Many of these packages are now fl ip-chip area-arrays instead of peripheral wire-bonding pad geometries.
PWB and Interposer Wiring Roadmap
A way to look at IC packaging design rules is shown in Figure 5, the packaging feature roadmap. The pitch of various packages, from 1.27 mm to 0.08 mm, is broken out by the design rules required to connect them up on a PWB. The largest pitches are ball grid arrays (BGA) to 0.8 mm. Then, from 0.65 mm to 0.25 mm, they are chip-scale packages (CSP). Below 0.25 mm is the region of direct chip attachment (DCA).
The Classic Multilayer
The classic multilayer is now over 40 years old. The design rules are different, but not by much! If you look at the 1968 16-layer multilayer that Hewlett-Packard used in its now historic HP-9100 desktop programmable computer (Figure
6), the ROM for that computer was created from a 16-layer FR-4 multilayer with sheets of PTFE introduced between the prepreg layers. The 0.150 mm traces and spaces were etched to create 1s and 0s that high-speed pulses could read through coupling, thus creating the 512 64-bit words of the basic operating system. The 100-step programs and variables were
stored in ferrite memory. This invention moved the computer from million-dollar, air-conditioned offi ce behemoths to "everyman's" desktop. The ROM PWB was required because ICs of that day had only 12 gates per chip-nowhere near the 32,768 bits (131,072 gates) needed for the operating system ROM. Contrast this to just three years later, 1971, when Hewlett-Packard reduced the desktop to a pocket-sized handheld calculator, the HP-35. This started the modern age of portable electronics.
Problems with Multilayers
Multilayer is a stagnant PWB design fl ow for the following reasons:
- Technology hasn't changed in 40 years
- Still signal, power, and ground
- Traces, spaces, and holes are smaller, but not by much
- FR-4 is still the major dielectric
- Current and future IC technologies are sensitive to multilayer TH capacitance and inductance
- High-performance, volume, cost-sensitive market segments (Consumer, Telecom, Automotive) have left classic multilayers for HDI-enabled technologies
- Pac Rim fabricators have 10 years' experience pushing the HDI/embedded envelope
- Component vendors' (especially IC) new products depend on HDI
- Decreased functionality and higher costs compared to HDI
North America is still the largest user of classic multilayers over 16 layers, as shown in Figure 7. Asia has tempered that use of classical multilayers with the use of HDI PWBs.
HDI Multilayer Platforms
HDI is such a large and growing PWB application market that it is made up of at least four different HDI platforms: (1) Substrates and Interposers; (2) Modules; (3) Portables; and (4) High performance. Chapter 2 will provide more detail about the HDI market.
Substrate and Interposer technology is used for fl ip-chip or wire-bondable substrates. Microvias offer the escape for very dense fl ip-chip area arrays. Dielectric is new-engineered fi lms. A typical example is seen in Figure 8. Chapter 16 will discuss these substrates in more detail Modules are small substrates that may have their ICs wire bonded, fl ip-chipped, or TAB mounted or may use fi ne-pitch CSPs. The discrete components are typically very small, such as 0201s or 0101s, and may even be embedded. The design rules are usually coarser than the single IC substrate, since the module may be larger than a single IC package. A typical example is seen in Figure 9. Chapter 16 will discuss these modules in more detail.
Portables and miniaturized consumer products are the leading edge in HDI technology. Their dense designs offer small form factors and very dense features including microBGA and fl ip-chip footprints. Typical products are seen in Figures 10 and 11.
High-performance technology is used for high-layer-count boards with high I/O or small pitch components. A buried via board is not always necessary. The microvias are used to form the escape area of dense components (high I/O, micro BGA). Dielectric is reinforced resin-coated foil, reinforced prepregs and cores and high-performance laminates. A typical example is seen in Figure 12.
A possible fi fth HDI platform is for embedded components, either planar or discrete. Figure 13 shows a simple example of how HDI is used to connect embedded components. Chapter 14 will discuss embedded components in more detail.
HDI Opportunities and Drivers
The advantage of higher density and electrical performance comes home when creating a new product! System optimization, as seen in Figure 14, can balance the trade-offs of gains and losses in various technologies while meeting critical schedules, achieving projected performance, and managing costs so that the product will be successful.
These fi ve technologies: Circuits, Components, Materials, Design and Manufacturing processes, as well as many others not mentioned here, are the Measures of Excellence.
Performance Improvements
When performance improvements are required for PWBs, HDI is the leading contributor. In addition to making the PWBs smaller, lighter, and thinner, HDI will give them superior electrical performance. Some of the performance improvements are:
- Lower order of magnitude via electrical parasitic
- Minimal stubs
- Stable voltage rail
- Removal of decoupling capacitors
- Lower crosstalk and noise
- Much lower RFI/EMI
- Closer ground planes
- Closer distributed capacitance
- Surface ground planes with via-in-pads cut emissions
Related to IC technology and smaller gate geometries is the increasing speed of signals which manifests itself not just in higher-frequency applications, but also in shrinking signal rise times. Another result is higher heat dissipation and a consequential reduction in power supply voltage. All of these conspire to increase the sensitivity of circuits to various forms of noise and loss of signal strength. Newer highperformance materials, with higher thermal resistance (for lead-free soldering) are being invented to solve these problems. Additionally, improved processes for microvias improve highfrequency performance.
An HDI test vehicle is an ideal platform to test electrical performance and signal integrity structure stack-ups before they are used on a product. Microvias have nearly one-tenth the parasitics of THs. These structures can validate the lower inductance in microvias and, when combined with lowinductance decoupling capacitors and via-in-pads, show the merits of noise reduction in high-speed but reduced-voltage designs. Other simulations and test vehicles have already proven the advantage of HDI at higher frequencies. Figure 15a shows the simulation from AnSoft of the typical 0.33 mm (0.013" FHS) TH in 1.6 mm thick (0.062") FR-4. Figure 15b is
the same simulation, using a 0.15 mm (0.006") microvia, 0.100 mm deep (0.004"), where the microvia has fewer refl ections and a much larger frequency tolerance than does the TH. The lower inductance of a microvia (~30pH) is useful when coupling to power and ground, especially above 1.5 GHz, for decoupling capacitors. A typical TH will have an inductance of at least 2-3 nH, and this inductance will inhibit the performance of decoupling capacitors in the GHz range as seen in Figure 15.[3]
Access to Advanced Components
The semiconductor industry is the primary driver for electronics. Smaller gate geometries and greater total gates allow more functions to be performed at a faster rate. With larger wafers, the prices continue to tumble. This allows and inspires more products that grow the entire industry. We (the U.S.) are still the drivers of advanced semiconductor technologies. Much of the foreign construction of wafer fabs has focused on commodity memory and glue chips. IBM, Intel, Motorola, AMD, Sun, H-P, and Texas Instruments, to name just a few, are continuing to lead the IC industry worldwide.
IC packaging, say a 1.0 mm pitch device, benefi ts from PCB technologies like HDI, but the use of 0.8 mm pitch devices is where HDI really begins to provide advantages. The blind vias save room on inner-layers and have reduced via lands, and make via-in-pads possible. Typical of these devices is the 296 pin, 0.65mm pitch, Digital Signal Processor (DSP) (Figure 16a) or the 257 pin DSP shown in (Figure 16b). Other new components becoming more widespread are ones with very high pin counts of around 600 to 2500, even at 1.27 and 1.0 mm pitches. Although some of these are telecom digital switches (Figure 16c), the vast majority are the new fi eld programmable gate arrays (FPGAs). Current products from Actel, Infi neon, Xilinx, and Altera have packages with 256, 348, 396, 456, 564, 692, 804, 860, 996, 1020, 1164, 1296, 1303, 1417, 1508, 1696 and 1764 pins (see Figure 17).
Faster Time-to-Market
Faster time-to-market is the result of easier placement of components using blind vias or via-in-pads. Other design efficiencies come about because of smaller spacing, improved BGA breakouts, boulevards routing (see Chapter 3), and ease of auto-routing using blind/buried vias over TH vias. The overall system design times can be reduced because of the improved
FIGURE 16: Fine-pitch devices such as this 948 pin - 0.65 mm pitch microprocessor, the 498 pin - 0.5mm DSP device or the 480 pin - 0.4 mm controller, even the 182 pin - 0.25 mm require microvias. The 2577 pin - 1.0 mm pitch digital switch now requires microvias in order to connect them on a printed circuit.
electrical performance of blind vias instead of TH vias and the fewer respins required because of signal integrity and noise reduction (see Chapter 4).
Improved Reliability
Extensive reliability testing was performed by the IPC-ITRI in the late 1990s about the reliability of microvias.
Other groups (like HDPUG & JPL) have also produced reports on the superior reliability of small-blind vias over TH vias. Understanding why is quite simple! The via aspect ratio (AR-depth to diameter ratio) is less than (<) 1:1 compared to TH which has an AR of >6:1 that goes as high as 20:1. This
is a result of the thin materials and low Z-Axis TCE materials used in HDI (see Chapter 5). HDI materials are numerous and exceed multilayer laminate in variety, thus they are covered by the IPC Standard IPC-4104A and not IPC-4101B. If the blind vias are properly drilled and plated, they will perform with many times the thermal cycle life of typical THs (see Chapters 7, 8, 10 and 12).
Thin HDI materials are thus suited for thermal heat transfer as covered in the IPC HDI Design Standards, IPC-2226.
Lower Cost
Chapter 3 will discuss in detail the improved design process for HDI PWBs. Properly planned and executed, an HDI multilayer can be less expensive than the TH board alternative as illustrated in Figure 18, comparing the benchmark of a high-speed, controlled impedance 12-layer TH multilayer to an 8-layer HDI multilayer. By fully utilizing the Secondary Side
FIGURE 18: The Benchmark redesign of the 12-layer TH controlled impedance multilayer on the left results in the 8-layer HDI multilayer on the RIGHT. In addition, 40% less space is required with the HDI board due to the microvia-in-pads.
of the PWB, 40% less area was required to connect all of the components, in addition to four fewer layers. The Obstacles in HDI implementation Historically, there have been a number of obstacles in implementing HDI. These obstacles form implied risks to using the technology. One of the major goals of this HDI Book is to eliminate those obstacles and risks, such as:
Predictability
Customers need to know the HDI stack-up, DRs, and price, before starting the project or design. Fabricators will often quote the design after it is designed, but without the numbers up front, no one can afford the time to run down a blind alley. The concept that microvias cost more is based on a lack of knowledge of how to properly design an HDI board.
Design Models
We have accurate wiring models that can take basic component data, schematic info and board size to create a stack-up and design rules. Very few fabricators have learned the technology of simulating a fi nished PWB!
CAD Tools
Few fabricators have designed an HDI board, so they are unaware of the changes and new procedures required for their CAD tools. Stack-up, architectures, channel routing, and boulevard routing are new developments in design that most designers have not heard of, so they don't know where to start!
Signal Integrity
Users are not aware of the electrical performance improvements that HDI can offer or the problems THs are creating.
Volume Production
Most volume HDI fabricators focus on cell phone and consumer products. Many fabricators need to focus on low volume HDI needs as well.
New Materials
HDI has introduced new materials that users are very unfamiliar with (RCF, liquids, and vacuum-laminated fi lms).
Assembly Issues
Many assembly people have never seen via-in-pad (VIP) or (VIL) before and think they will steal solder-paste from the joint. They won't. Volume is less than 1% of the solder paste brick. Forcing VIP to be ‘fi lled & fl ush' needlessly adds 8%-15% to the price. Putting the dogbone back in an HDI board takes up area and adds a great deal of inductance to the circuit (~25 nH per inch).
Assembly Test
Using VIP and blind vias, there are no THs on the back side to use as test points. Density is so high that there is no room for large 0.050" pads as test points. Reduced test point accessibility is a new concept that many have not adjusted to yet. This book will tackle all eight issues and present the education and solutions to these implied risks.
Predictability or ‘What Will It Cost?'- the Need For Design Models
I have been working with HDI boards since 1983, when Hewlett-Packard built its fi rst microvia multilayer prototype, the Finstrate. It took many years before we learned how to design with the technology effi ciently due to all the different options in stack-up, via structure, and design rules that could be employed. We fi nally developed a predictive ethodology that allowed us to plan the design and select the best stack-up and HDI architecture (Figure 19). The details of this methodology can be found in chapter 19 of the sixth edition of Clyde Coomb's Printed Circuits Handbook from McGraw-Hill.[6]
Software to execute this "HDI Planning Methodology" has been developed four times. The fi rst was MCC's Multichip Design Advisor-MDA which spun off Savansys which eventually created Savantage. Neither organization exists today. Hewlett-Packard Laboratories created the "PCB Design Advisor-PDA" and then "Explorer" to optimize the choices and constraints of the PDA. Finally, I created my own "PCB Advisor" that I have used for many years for HDI consulting (Figure 20).
One of the outcomes of this simulation, as well as many Benchmarking activities (Figure 18), was the TH versus HDI Trade-Off chart seen in Figure 21. In the Price/Density
FIGURE 19: HDI Predictive methodology is used before the actual physical design in order to select the appropriate layer stack-up, via architecture, and design rules. Only the schematic, BOM, and estimated design rules are required.
Comparison, the two key variables are RCI (a comparison currency normalized to the actual price of an 8-layer multilayer) and DEN (the average number of pins on a board divided by the length and width of the board).
The RCIs in the matrix are the fl oor numbers (minimums). But the ceiling numbers for a range are not within our ability to calculate or set up at this time. The maximums are practically limitless, depending on various factors in the design. Yields are very sensitive to minimum diameter, annular rings, minimum trace and spacing, material thicknesses, total number of holes, and their density. Other cost factors, such as fi nal fi nish, hole fi lling, and tolerances will affect the price. I have added a column for "Density" (DEN). This is the Maximum Number of Electrical Connections (called ‘pins') per square inch of surface (for both sides). The dashed lines are equivalent PCBs. So, as an example, an 18-Layer TH (through
hole-Column A) board with an average of 100 pins per square inch (p/si) could have been designed as a 10-layer HDI board (1+8+1-Column C) because it can handle 210 p/si. Or, it could have been designed as a 6-layer HDI board with 2+2+2 (Column E, also 200 p/si).
The RCI does not show the absolute cost savings in this example. The relative cost savings is 28.1% for the 10-layer and 20.5% for the 6-layer HDI equivalents. A smaller board could result in more boards per panel and the price would be even lower than the above numbers. In the range of 8L to 18L, the HDI boards, especially the 2+N+2 are not the equivalent of 8L to 18L TH boards. They represent boards with 12 to 20 times the density of TH boards. Even the 1+N+1 HDI boards represent TH boards with 14L to 30L layers!
This matrix, which is based on FR-4, has two important implications. The TH RCI scale (4L - 16L) represents
competitive pricing set by China. This scale is depressed compared to the HDI pricing. So the HDI pricing, if equal or lower, is very competitive. If the material of construction is not FR-4, but a more expensive, low Dk or low Dj material, then the savings from HDI will be much larger as you reduce layers!
Design Tools - CAD
EDA tools for HDI have been slow in coming. Fortunately, they are available today and continue to improve. Important differences and additions that are required from conventional
TH EDA tools (Figure 22) are:
- Blind and microvia structures of staggered (adjacent), stacked (coincident) and inset structures
- Any layer and layer-pair stack-up structures
- Blind/buried via spacings
- Component breakout and breakthrough for via-in-pad
- Any angle routing
- BGA fanout automation
- Dynamic via and component trace entry
- Via push and shove
- Auto-routers optimized for blind/buried vias
- Links to electrical, thermal, and FPGA simulation tools
- DRCs for HDI structures
- Localized rules under components
More details about EDA tools will be discussed in Chapter 3 - HDI Design, as seen in Figure 22. How complex BGAs are fanned out and broken out to create boulevards for improved routing is an important part of that chapter.
Electrical Performance and Signal Integrity
Tightly linked signal integrity, power integrity tools, and HDI layout tools provide insight into the superior electrical performance of HDI structures. With the faster rise-times of modern ICs, board parasitics that we used to ignore are now very important.
These board parasitics are shown in Figure 23 and include: power and ground plane capacitance and inductance, package capacitance and inductance, Circuit Board A connector capacitance and inductance, backplane or cabling capacitance and inductance to board B, and how Circuit Board B's connector and board capacitance and inductance, power and ground plane capacitance, and inductance are structured. This will be discussed in Chapter 4, as well as the infl uence of vias in electrical performance.
The electrical infl uence of vias in high-speed nets cannot be overlooked. THs have parasitic capacitance and inductance and can be a signifi cant factor in signal performance. The lumped model of a TH has nearly 10X the parasitic value of a microvia (Figure 24).
Fortunately, signal integrity and power integrity EDA tools
FIGURE 25: Electrical performance and signal integrity simulation of differential microvias. Displays are signal and impedance, losses, and an eye diagram. (Source: Mentor Graphics' HyperLynx)
Fabricator Capability
As of 2008, the roster of North American PWB fabricators includes 135 that will produce HDI multilayer, as disclosed by the FAB FILE [7]. Further analysis of that database shows that only 95 actually own their own laser drill. Creating and maintaining HDI processes is notoriously expensive and requires a great deal of engineering experimentation and control. Later chapters deal directly with the "how-to" of HDI fabrication.
The IPC has created a number of new "Hands-On" Programs, in partnership with the U.S. Navy's CRANE NWS high-technology PWB/HDI facility in Crane, Indiana.[ www.ipc.org ]
New Material
Laminates are increasingly important to high-performance PWBs. Low loss laminates as well as low dielectric constants (or consistent dielectric constants) are both critical. Higher heat resistance is needed for lead-free assembly processes. The new feature that laminates need is a higher Decomposition Temperature (called Td). This is the temperature that a laminate can withstand when it has lost 5% of its weight by thermal gravimetric analysis (TGA). This is an ASTM D 3850 Test Method. Even 2-3% loss, especially when exposed to multiple thermal cycles, can seriously degrade reliability.
Other new laminate features are uniform glass to laser drill easier, thinner glass for better electrical properties, thin and high dielectrics for distributed capacitance between power and ground, and a plethora of laminates with embedded passive layers to form resistors (Figure 26) and/or capacitors.
But like PWB manufacturing, our dominance here is eroding. Currently, Matshushita (Japanese) and NanYa Plastics (Taiwan) are number one and number two in the world in FR-4 sales and manufacturing while North America still dominates in specialty high frequency laminates. All of these HDI materials are discussed in more detail in Chapter 5.
Other important materials for HDI are via-fi lling. As seen in Figure 27, electrochemical plating to fi ll blind vias as well as two-part epoxy, conductive or not, can be used to fi ll vias. This is discussed in Chapter 10.
Assembly Issues
Two important assembly issues are assembling and soldering open blind vias-in-pads and providing for assembly in-circuit testing. Only the open via-in-pad, created by conformal plating is of concern in assembly (Figure 27). Filled vias will solder as normal-fl at lands. HDI assembly issues are discussed in Chapter 13.
Assembly Test
The DfT Process and how it interrelates with the PWB Design Process can be seen in Figure 28. DfT software enables test engineers to work concurrently with designers. They can predict the fault spectrum, plan test strategies, understand fault coverage, and test access tradeoffs prior to the layout/routing stage of PWB design. This is important because of the cost versus volume considerations in product testing. Some types of software predict a fault spectrum for every pin, component, and signal on the board and thereby identify which test pads will provide the greatest test coverage. By listing the test pads that provide the greatest test coverage in descending order, designers can make intelligent decisions on which test pads should be provided on boards with limited access. Furthermore, if the software models the fault coverage provided by each machine in the distributed test plan (AXI, AOI, ICT, etc) it can identify which test pads can be removed
because of overlapping fault coverage from other test stages.
This is covered in greater detail in Chapter 13.
HDI Value Delivery Chain
While HDI substrates are one the fastest growing technologies in electronics packaging worldwide, they are not the simplest to embrace. Implementation requires a coordinated engineering approach, sometimes referred to as the HDI Value Delivery Chain (VDC). This chain has six links (Figure 29):
- System Partitioning Circuit Design
- PCB Design PWB Fabrication
- PWB Assembly Assembly Test
These technologies must be present and coordinated in order for a successful HDI product to be realized. The successful integration of HDI technology will result in improved product performance, cost competitiveness, and new product innovations.
System Partitioning: When a new product is conceived, one of the fi rst activities is to break the product down into components or partitions that will allow it to be designed, manufactured, sold, and supported. This is extremely important since a mistake here may result in a product which lacks the right features, costs too much, or arrives on the market too late. Partitions vary but may include the size, weight and volume. They also include distribution of standard active and passive components or custom ASICs, packaging of parts, number and size of printed circuits, and how they connect to each other. HDIS needs to be considered from the very beginning in order to take advantage of the benefi ts listed above. Applied later in the design process, the advantages will not be as great or may not even be available! Features, components, risk management, and manufacturability have to weighed and traded off in order to have a successful product.
Circuit/Product Design: The bulk of product creation and design involves the logic design, circuit simulation, component selection, custom integrated circuits, and mechanical designs. HDIS offers advantages in electrical and thermal performance. The key to value is the ability to simulate the improved electrical and thermal characteristics of the many HDIS options without which, the HDI structure looks like any other TH board.
PCB Design/Layout: Many challenges have to be faced when designing an HDIS board. The wiring models are important to know in order to select proper design rules and constructions. With blind and buried vias, the HDI structures are more varied and complicated than conventional boards. Knowing what is cost effective from a design-for manufacturing perspective is essential.
Special design rules must be considered with HDI structures. Each manufacturing process may have special considerations and limits. Design tools, pad stacks, and auto-routers are all used differently in HDI designs. The customization of the design process is not a common activity yet. The newer CAD systems have expert systems available that provide much needed advice. Manufacturability audit software concludes the layout process with a thorough check for any mistakes or errors.
PWB Fabrication: Of the entire value delivery chain, fabrication has become the most established. Currently over sixty companies worldwide are using at least twenty different processes to essentially make the same HDI structures. Making the microvia is the easy part, since lasers, etchers and photodielectrics have been rapidly improving over the years. The challenges are the basics: registration, fi ne line lithography, metallization, and plating. On HDIS, all of these have to perform at a superior level. While this is certainly taxing, it benefi ts all printed wiring board manufacturing processes.
The one area of HDIS fabrication that has lagged behind is electrical test. We can fabricate much fi ner geometries than we can cost effectively test.
PCB Assembly: Assembly has new value to deliver with HDIS. Components can be closer together, which can change refl ow profi les and repair. As the top side fi lls up, the opposite side has to take more components including many active ones.
This will alter the assembly process and refl ow profi les. With newer smaller and denser area array components like chip scale packages or fl ip-chips, the total number of connections per square centimeter increases dramatically. These newer smaller components with underfi ll or very high surface connection densities may have a reliability interaction with thinner HDI structures. Thin structures are more likely to flex during thermal cycles and this introduces new mechanisms and opportunities for failure, which must be thoroughly evaluated and tested.
Assembly Test: The final stage of the HDIS value chain is assembly level test which presents new issues with HDIS and the new smaller area array components. If via-in-pads are used with the area array components, after assembly there are no breakout vias to use to test probes. Design-for-Test becomes a major ingredient for system partitioning. Testing from the perimeter, boundary scan, or built-in self-test becomes a major design factor. Components may be so close now that test pads are either too large or there is no room to get a test pin into the area. Adding test pads to the surface after the board is designed can add to its complexity and cost and add detrimental parasitics to the circuit. Newer assembly level verification schemes will probably be developed that do not require the classical bed of nails fi xtures, replacing them with faster non-contact test techniques.
Basics of HDI Technology Metrics
Interconnect Density
When planning an HDI design, there are three linked measures of performance or metrics for the HDI process. The measures of performance or metrics for the HDI Value Delivery Chain (VDC) are important concepts for they capture the three elements of interconnection:
Assembly Complexity: Two measures of the difficulty to assemble surface mounted components. Component Density (Cd),measured in parts per square inch (or per square centimeter) and Assembly Density (Ad) in leads per square inch or per square centimeter.
Cd = p/a Equation 1
Ad = l/a Equation 2
Integrated Circuit Packaging: The degree of sophistication of components, Component Complexity, (Cc), measured by its average leads (I/Os) per part. A second metric is component lead pitch.
Cc = l/p Equation 3
Printed Wiring Board Density: The amount of density (or complexity) of a printed circuit (Wd) as measured by the average length of traces per square inch of that board, including all signal layers. The metric is inches per square inch or centimeters per square centimeter. A second is the number of traces per linear inch or per linear centimeter. The PWB density was derived by assuming an average of three electrical nodes per net and that the component lead was a node of a net. The result was an equation that says the PWB density is β times the square root of the parts per square inch times the average leads per part. β is 2.5 for the high analog/discrete region, 3.0 for the analog/digital region, and 3.5 for the digital/ASIC region:
PWB Density (Wd) = β √[Cd] x (Cc)
= β √[(parts per sq. in.)] x (ave. leads per part)
Equation 4 [9]
Where:
p = Number of components (parts)
l = Number of leads for all the components
a = Area of the top surface of the board (square inches)
A new metric for Wiring Density is the connect, as seen in Figure 30. A connect is defi ned as the SMT pad, the via pad and the trace connecting the two. Only so many connects can be placed in any defi ned area. The maximum connects are what defi ne the red and blue dashed lines in Figure 31. This is the "Through-Hole Barrier."
Packaging Technology Map
Figure 31 is what I call a Packaging Technology Map. The Packaging Technology Map was fi rst displayed by Toshiba in January of 1991 in their paper, "New Polymeric Multilayer and Packaging" at the Printed Circuit World Conference V in Glasgow, Scotland.[10] I didn't invent this chart, but I have been unsuccessful since 1991 in fi nding the Japanese who did. No one in Japan seems to know about this chart!! By charting products of a particular type over time, an analysis shows how the packaging technology is changing, its rate of change, and the direction of those changes. This is the exercise of roadmapping! But now, the exercise will have some data behind it.
A second valuable feature of the map is the area of upper right. I have called this the "Region of advanced Technologies." This is where calculations and data have shown
that it is necessary to have an HDI Structure. The dashed lines indicate the barrier or wall of HDI. Cross this and it now becomes cost effective to use HDI. Move too far and it becomes a necessity.
To create the packaging map, an assembly is measured for its size, number of components, and the leads those components have. The area is the laminate not the surface area. The components include both sides of an assembly as well as edge fi ngers or contacts. By the simple division of leads by parts and parts by area of the assembly, the X- and Y-axis are known. Plotting the components per square inch (or components per square centimeter) against average leads per component on a log-log graph, the PWB wiring density in inches per square inch (or centimeters per square centimeters) and Assembly Complexity (in leads per square inch or leads per square centimeter) can be calculated. The Assembly Density is just the X-axis multiplied by the Y-axis.
Through-Hole Wiring Barrier
When the Packaging Technology Map is used to analyze surface mount assemblies, three major zones show up which is why I call it a map. The fi rst group includes products with a high content of analog devices and discrete components, such as camcorders, pagers and cellular telephones (C-C'). They have the highest assembly complexity, up to 300 to 400 leads per square inch (47 leads per square centimeter). The second group includes products with a high degree of digital components and some mixed discretes, such as notebook computers, desktops, instruments, medical equipment, and telecom routers (A-A'). The last group has a highly integrated use of ICs, such as PCMCIA, fl ash memory, SiPs, and other modules (B-B'). This group has the highest PWB wiring density of over 160 inches per square inch (25 centimeters per square centimeters).
When you look at the Packaging Technology Map, the Assembly Complexity lines cross the Wiring Density lines. At high discrete levels, less wiring is required for the amount of assembly density. At high ASIC (and low discrete) levels, much more wiring is required to connect the components. This makes assembly metrics like leads per square inch a good indicator, but not adequate to substitute for the PWB wiring density.
If you travel any one of the three cords (A,B,C to A', B',C') and distribute the total leads per square inch into signal layers, Figure 32 shows the signal and total layers required to wire up that number of leads per square inch. Because of the space limitation of TH pads, as well as SMT lands of 1.27 and 1.00 mm pitch BGAs, the number of layers turns up exponentially around 130 p/si.
In contrast, HDI design rules and number of layers (Figure 33), at 130 p/si, require only ten layers. Even at 300 p/si, only 20 layers are required.
HDI Layout
The three layout metrics are:
- Layout Efficiency - a measure of the amount of traces on an inner-layer as a percentage of the maximum that could be on this I/L.
- Routability Predictor - a measure of how easy it is to route the selected traces (at their designated design rules) into the remaining space available.
- Routing density - inches of traces per square inch of inner-layer or cm of traces per sq. cm.
The equations for these can be found in Coomb's Printed Circuits Handbook, sixth Edition, Chapter 19.[6] The HDI Value Delivery Chain will use these metrics to establish many more relationships.
How to Get Started
After reading this book, it is our hope that you will consider using HDI technology for your next PWB design. To help you get started, we recommend a four-phase approach (Figure 34):
- HDI Technology Education
- Test Vehicle Evaluations
- Redesign Existing TH Board
- New Production
First, become familiar with HDI technology and identify your HDI fabricator. Their capability is your fi rst concern. For a bit of advice, consider referencing the IPC Benchmarking Program, PCQR2 which provides a set of standardized artwork, for 2 to 24 layers, and a very rigorous electrical testing regimen (including thermal cycling). The artwork and sample report
are available at, http://www/pcbquality.com. Details and a review of this IPC Program are covered in Chapter 12 - Quality, Acceptability and Reliability. If questions persist about design rules, electrical performance, or reliability, then consider creating a simple Test Vehicle. To establish the design rules and HDI design methodology, consider the redesign of an existing high-density TH board using the advice in Chapter 3 - HDI Design. Finally, with this background and experience, HDI can be applied in the most favorable way.
HDI Technology Education
There are a great deal of technical details involved in using HDI technologies. Hopefully, this book will provide insight and education in this endeavor. PCB fabricators need to be involved and characterized for their HDI capability and prepared to accept your designs. Their DFM information may change your designs or stack-ups.
FIGURE 34: Getting started in HDI can involve four phases of learning and development.
Test Vehicle Evaluations
The PCB vendor may not be familiar with the materials you have designed with or you may need to test some of the many new high-temp or high performance materials listed in Chapter 5 - Materials. This is a good time to test highfrequency performance and measure the signal integrity improvements. Reliability can be tested for the HDI stack-up, materials, and fabricator selected.
Redesign Existing TH Board
Simultaneously, a recent high-density board can be redesigned to an HDI structure to test assembly, performance, Introduction to High-Density Interconnects
ICT and any other issues. It may not be necessary to fabricate this redesigned board, but if components are not moved, samples can be assembled and tested. If the redesigned board does not take advantage of distributing parts on the secondary side, then only the BGA fanout, boulevard routing and stack-up changes can be evaluated. Additional size and routing advantages will have to wait until the fi nal phase implementation.
New Production
Once all the questions and issues are resolved, design tools mastered, and vendors qualifi ed, the HDI technology can be freely implemented.
For more information visit http://hdihandbook.com/.