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Basic Impedance Fabrication Guidelines, Part 1
June 10, 2009 |Estimated reading time: 4 minutes
Today's column covers some very basic impedance guidelines for fabrication. Here's a very brief recap of what I said in my previous column: Prior to trace routing, pre-establish the effective Dk of each sub-section with your chosen fabricator.
Remember that, generally, the thinner the dielectric, the thinner the pre preg or b-stage, and the thinner the b-stage, the higher resin content. The higher the resin content, the lower the Dk. This will help you model the impedance structures more accurately and design for 10%. Enough said.
Now, when we talk about signal integrity or impedance lines, there are some very basic guidelines to follow. I will describe some of the practices and guidelines that will help you to meet your basic impedance needs. There will be more on signal integrity in future articles.
Why Should I Design For 10%?
Designing for 10% is critical when, for instance, designing a six-layer board, where many times there are Impedance signals sharing the same reference planes. A common stackup is SIGNAL-PLANE-SIGNAL-SIGNAL-PLANE-SIGNAL. If, for instance, layers 1, 3, 4 and 6 are all impedance-controlled, all dielectrics are predicated upon one another as 1 and 6 share the same ref planes as 3 and 4.
Make sure the impedance-controlled signals have proper reference planes. Avoid having more than two signals between two ref planes. This can create unwanted noise/EMI issues. When routing the second signal on an internal layer, a good practice is to orient the traces 90 degrees from the first signal so the cross-section of coupled traces is minimized. (Route one set of signals horizontally and the next vertically to minimize crosstalk.)
I see many designs that do not have a ref plane for the entire length of the run of the intended signal as well. Basically, make sure the ref plane encompasses the entire structure.
When doing SIGNAL-SIGNAL-PLANE construction and the external signal is "passing through" the traces on layer 2 to reference layer 3, remember: The further away from the ref plane you get, the wider the surface trace needs to be. Again, route the traces 90 degrees to the next signal to minimize noise. Obviously, this won't work for boards that are at a "real estate premium" since again the surface traces must be wider to deal with the ref plane deeper in the stack.
When doing "broadside" type impedances, create the stack in such a way that the two broadside signals reside on either side of the SAME core to minimize any offset. If the two broadside signals reside on two separate cores, any lamination misregistration issues can create an unwanted offset.
Many times customers will unintentionally induce co-planar coupling by having the copper pour for plane areas too close to the impedance tracks.
Avoid having copper pour for plane areas closer than 3x the intended trace width, unless you are intentionally inducing co-planar coupling (more on that in Part 2 of this series). Note: The 3x rule is just a rule of thumb. The larger the trace width, the less distance to ground separation before inducing co-planar coupling.
This one is a common issue at the fabrication level, especially when board real estate is at a premium. In other cases, sometimes we see coupling on both sides of the trace, sometimes on only one side, and sometimes in "free space."
What if all three scenarios are present on the same layer? In that case, we will ask the customer if he intended any co-planar coupling. If the answer is no, we will calculate as uncoupled, remembering to pour copper on the impedance coupon that resides on the panel periphery so that the coupon itself is not overplated and remains representative of the part.
Differential Pairs
When designing differential pairs, make sure the space between the tracks is consistent for the entire length of the run. This is a common mistake at trace routing - the long sections of the runs themselves may indeed have the same space, but when a corner is turned the space goes out the window.
Also, for diff pairs, match the lengths of the routed pairs. Sometimes this means extending one of the traces with a serpentine pattern to match the length of the other trace. Avoid using the same trace size for two impedance scenarios. (For example, using .007 lines for part of a diff pair scenario and as single-ended structures) Differentiate between the two scenarios by a tenth of a mil - make one of them .0071. This tenth of a mil cannot be resolved by a manufacturer but it helps us uniquely select the single-ended structures from the diff pairs in case they require resizing. Likewise, avoid using the same draw size for both traces and copper pour for the same reason.
That's it for now. In my next column, we'll talk about the use of net lists to verify the design criteria against the provided Gerber artwork files.
Remember, impedance mismatches cause signal reflections, which reduce voltage and timing margins.
Mark Thompson provides engineering support at Prototron Circuits. He can be reached at MarkT@prototron.com.