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3D Packaging Realities the Focus of New IPC Conference
August 28, 2013 |Estimated reading time: 2 minutes
The trend to squeeze multiple chips into a package may create a new market category for board fabricators and EMS providers. Those who can make thin, flat boards that have fine lines may be able to capitalize on the transition to 3D packaging.
The high cost of very high density semiconductors is prompting more OEMs to turn to system-in-package (SIP) technologies. These concepts, which have been around for years, are seeing increased use now that silicon and substrate technologies have advanced. “A lot of companies are focusing on advances in multichip modules and system in package technology,” said Ron Huemoeller, senior vice president for advanced product development at Amkor Technology. “The concept has been picking up steam with the advances in through-silicon vias (TSV). Ultimately, the organic substrate suppliers will have a role to play in this new area as well.”
TSV is emerging rapidly as more silicon makers and packaging providers learn how to work with the fine lines needed to connect bare die that are stacked atop each other. Getting substrates that provide both fine line geometries and low costs are among the main challenges facing the developers of these high density packages. Huemoeller believes this creates market opportunities for those willing to take a chance and enter a market that has major growth potential.
“Some substrate suppliers are making investments,” Huemoeller said. “They need higher grade materials and equipment with better lithography, like steppers. They also need to take advantage of plating improvements.”
Bringing SIP and TSV into the mainstream will require advances in other areas as well. Tolerances will be much tighter as line width requirements shrink. “Different materials that are flatter and smoother will be required to produce sub 5 micron lines and spaces,” Huemoeller said.
He’ll be expanding on these concepts at the IPC Conference on Component Technology: Closing the Gap in the Chip to PCB Process. Huemoeller is the keynote speaker at the conference, which will take place September 10-12, 2013, in Chandler, Arizona.
The conference will include a broad range of views. An Intel design manager will divulge the chipmaker’s views on the future of packages for computing electronics. Market researchers from TechSearch International, Prismark Partners, and N.T. Information Ltd. Will provide their observations on market potentials for these products. A number of specialists from throughout the packaging and outsourced semiconductor assembly and test industries will also be presenting at the conference.
Though 3D packaging and SiP are a couple of the leading technologies and trends that will be examined at the conference, they aren’t the only new packaging concepts. Embedded components is another concept that’s starting to move from research and limited markets into broader applications. Huemoeller noted that manufacturers must develop refined processes if they want to compete in the embedded components arena.
“You don’t want to put known good die into poorly yielding substrates,” he said. “Manufacturing plants will have to have very high yields after die are placed into the substrates.”