Happy’s Essential Skills: Design for Manufacturing and Assembly, Part 2
Editor's Note: This is the second part of Happy’s Essential Skills: Design for Manufacturing and Assembly column, CLICK HERE for the first part.
The Role of Metrics For Predicting and Planning
Metrics are data and statistically backed measures, such as T-downs, Connectivity, Wiring Demand, Wd. These measures can be density, connectivity or in this context, producibility. These measures are the basis for predicting and planning. When used in the design process, there are three categories of measures applied to a product. Only the metrics can be shared by all in the design team. The non-metrics provide little assistance in design:
- Metrics: Both the product and the process are measured by physical data using statistical process control (SPC) and total quality management (TQM) techniques. (Predictive Engineering Process)
- Figure of Merit: Both the product and the process are scored by linear equations developed by consensus expert opinion. (Expert Opinion Process)
* Opinion: Opinion, albeit from an expert, is applied after or concurrent with design. (Manufacturing Engineering Inspection Process)
* No Opinions: No attempt to inspect or improve the design is done during the specification, partitioning, or design stage. (Over The Wall Process)
Metrics also establish a common language that links manufacturing to design. The "producibility scores" form a non-opinionated basis that allows a team approach that results in a quality, cost competitive product (Figure 8). Metrics allows design to progress through the “Engineering Design Ages.”
- Age of Anarchy (60%): anything goes.
- Age of folklore (25%): Wisdom is passed from one generation to another, over pizza and beer.
- Age of Methodology (10%): The way DFM is to be engineered is documented, and is actually done that way, using Figures of Merit.
- Age of Metrics (4%): Both the product and the process are measured in standard ways.
- Age of Engineering (1%): Productivity is achieve through continuous quality improvement, much like it is in manufacturing.
Figure 8: The benefits of metrics as a common design language.
The strategy in applying these measures is shown in Figures 9 and 10. The analysis process is unique to every individual and company, but certain conditions have to be met and considered if the product is going to be successful. If the score meets producibility requirements then select this approach, if not, then evaluate other opportunities and repeat the process. In the rest of this column, measures and metrics will be introduced that provide insight for layout, fabrication and assembly planning.
It is always preferred to have metrics when discussing producibility. But if metrics are not available, then the opinions of experts are better than nothing (no opinions). The problem with opinions is that they are difficult to defend and explain and, when used in conjunction with producibility, many times they vary with each person. Sometimes, the opinion process is implemented for good intentions by taking experienced production experts and having them review a new design. This is the expert opinion process and although it is sometimes successful, it is difficult to replicate and many times results in building barriers between manufacturing and design. That is why the Figure Of Merit Process is so popular. For a small amount of work by experts it produces a scoring procedure that can be used and understood by all. This was detailed in the last column, #9.
Figure 9: Process using “use of measures and metrics” to match a company’s design process to its manufacturing process and support culture.
Figure 10: Process to develop a Manufacturability Metric as a substitute for opinions.
LAYOUT TRADEOFF PLANNING
Predicting density and selecting design rules is one of the primary planning activity for layout. The actual layout of a PWB is not covered in these columns. The selection of design rules not only affects circuit routing but profoundly affects fabrication, assembly and test.
Balancing the Density Equation
What with the need for more parts on an assembly, or the trend to make things smaller to be portable or for faster speeds, the design process is a challenging one. The process is one of “balancing the density equation” with considerations for certain boundary conditions like electrical and thermal performance. Unfortunately, many designers do not realize that there is a mathematical process to determine the routing rules of a printed circuit. Let me briefly explain: The density equation, as seen in Figure 11, has two parts, the left side, which is the Component Wiring Demand, and the right side, which is the Substrate Wiring Capability (equation 2).
Component PWB Wiring Demand < PWBs Design Rules & Construction Wiring Capabilities Eq. 2
PWB Wiring Demand = total connection length required to connect all the parts in a circuit.
PWB Wiring Capability = substrate wiring length available to connect all the components.
Four conditions can exist between wiring demand and substrate capability:
- Wiring Demand > Substrate Capability: If the substrate capacity is not equal to the demand the design can never be finished. There is either not enough room for traces or vias. To correct this, either the substrate has to be bigger or components have to be removed.
- Wiring Demand = Substrate Capability: While optimum, there is no room for variability and to complete the design will take an unacceptable amount of time.
- Wiring Demand < Substrate Capability: This is the condition to shoot for. There should be enough extra capacity to complete the design on time and with only a minimum of overspecification and costs.
- Wiring Demand << Substrate Capability: This is the condition that usually prevails. By PC layout, the schedule is tight and timing is all-important. Many choose tighter traces or extra layers to help shorten the layout time. The impact of this is to increase the manufacturing costs 15−50% higher than is necessary. This is sometimes called the “sandbag approach.” It is unfortunate, since the models above would help to create a more planned environment.
Figure 11: “Balancing the Density Equation” to achieve an optimal layout.
Wiring Demand (Wd)
Wiring demand is the total connection length (in inches) required to connect all the parts in a circuit. When the design specifies an assembly size (in square inches), then the wiring density in inches per square inch or cm per square cm. is created. Models early in the design planning process can estimate the wiring demand. Three cases can control the maximum wiring demand:
- The wiring required to break out from a component like a flip chip or chip scale package
- The wiring created by two or more components tightly linked, say a CPU and cache or a DSP and its I/O control
- The wiring demanded by all integrated circuits and discreets collectively.
There are models available to calculate the component wiring demand for all three cases. Since it is not always easy to know which case controls a particular design, it is usually to calculate all three cases to see which one is the most demanding and thus controls the layout.
Wiring demand is defined as:
Wd = Wc x e (in cm/square cm or in./square in.) Eq. 3
Where: Wd = Wiring Demand
Wc = Wiring Capacity
e = PWB Layout Efficiency
Wiring Capacity (Wc)
Substrate wiring capacity is the wiring length available to connect all the components. It is determined by two factors:
- Design Rules—the traces, spaces and via lands, keepouts, etc., that make up the surfaces/layers of the substrate
- Structure—The number of signal layers and the combination of through, and buried vias that permit interconnection between layers and the complex blind, stacked and variable depth vias available in HDI technologies.
These two factors determine the maximum wiring available on the substrate. The maximum wiring times the layout efficiency is what is available to meet the wiring demand. The data is straightforward except for layout efficiency. Layout efficiency expresses what percentage of wiring capacity can be used in the design. The equation for wiring capacity for each signal layer is below. The total substrate capacity is the sum of all the signal layers:
Defined as: Wc = T x L / G (in cm/square cm or in./square in.) Eq. 4 
Where: T = number of traces per wiring channel or distance between two via pads
L = number of signal layers
G = wiring channel width or length between centers of via pads above
Layout Efficiency is the percentage of capacity from design rules and structure that a designer can deliver on the board. Layout efficiency is the ratio of the actual wiring on a layer that was used to wire up a schematic versus the maximum wiring that could be used on that layer (totally full) or Wd divided by Wc. Layout efficiencies, typically, for ease of calculations are assumed to be 10%. Table 2 provides a more detailed selection of efficiencies
Example of DFMA Metrics
Three examples I have from my early days of using DFM/A metrics was the design of HP’s first and second inkjet printer, the Thinkjet™ and Quietjet™, and the design of the next generation of standard paper color inkjet printer, the Deskjet™. The Dewhurst & Boothroyd Methodology was applied to the first prototype Deskjet (bb). This prototype evolved from the two earlier inkjet printers, only more complex because now the paper was cut-sheet and not fan-folded with sprocket holes and was color with two heads. In all aspects it was more complex, with complex assembly and consequently, a lower ‘Ease of assembly’ rating. As a comparison, HP evaluated competing IBM PROprinter and OKI 182 printers even though these were more expensive printers. The resulting redesign and optimization using DFMA principles and seen in Table 4 and the rating on the final Deskjet (lb)
Table 4: Results of DFM/A analysis of printer prototypes.
Figure 12: DFM/A analysis of three HP inkjet printers and two competitors.
- Boothroyd, G., and P. Dewhurst, "DESIGN FOR ASSEMBLY", Dept. of Mechanical Engineering, University of Massachusetts, Amherst, Massachusetts, 1983.
- General Electric, "Review of DFM Principles", Internal DFM Conference Paper, Charlottesville, VI, 1982
- Hawiszczak, Robert, "Integrating Design For Producibility Into A CAE Design Environment", NEPCON EAST, June 1989. pp 3-14.
- Holden, H., The HDI Handbook, published by PCB007, June 2008, a free download at hdihandbook.com.
- Boothroyd, G., and P. Dewhurst, "Design for Assembly", Dept. of Mechanical Engineering, University of Massachusetts, Amherst, Massachusetts, 1983.
- Daetz, Douglas, "The Effect of Product Design on Product Quality and Product Cost," Quality Progress, June 1987, pp. 63-66.
- Hume,H.; Komm,R.; and Garrison,T., IBM, "Design Report Card: a Method for Measuring Design for Manufacturability," Surface Mount International Conference, Sept, 1992, pp 986-991.
- John Berrie and Andy Slade, “Knowledge Based Design Analysis for EMC,” Publication of Zuken-Redac Systems Ltd., Tewkesbury, Gloucestershire, UK, 1995.
- O’Sullivan, Barry, “The Design Advisor: Capturing Design Practices and RFI / EMI Concerns,” The Board Authority, Vol.2, No.4, December 2000, pp. 47-52.
- Hanus, Robynne,” HDI DFM and Physical Design Verification,” The Board Authority, Vol.2, No.4, December 2000, pp. 42-46.
- L. Moresco, "Electronic System Packaging: The Search for Manufacturing the Optimum in a Sea of Constraints," IEEE Transactions on Components, Hybrids and Manufacturing Technology, 1990, Vol. 13, 1990, pp. 494-508.