Standard of Excellence: The Future is in Fine lines

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The age of much finer lines and spaces is upon us. After years of slowly moving towards this technology our customers are now demanding that all of us provide them with fine lines and spaces. Our new trend in electronics is for denser and denser circuitry on smaller and smaller real estate. Let’s face it, you just have to look at your typical smartwatch to realize you have an entire computer on your wrist; medical electronics where you have to build a small computer so small that you swallow it; a hearing aid so small that you can barely see it. This is where the world is not only going, but is actually there today.

And yes, these products dictate the need for fine lines, which in turn can be very challenging for those of us building these products. The routing of the lines between pads and vias necessitates this in localized areas as well as the drive to greater layer counts and subsequently thinner cores. All of this while maintaining 50Ω impedance. This is generally where lower Dk laminates can be of benefit to the designer and subsequently the fabricator. It allows one to use a wider line/space while maintaining the required impedance value.

Currently fine lines for standard production are 3-mil lines and 3-mil spaces (3/3). While the technology exists for ≤ 2.6-mil lines, achieving the surface finish necessary for achieving them reliably through imaging has been difficult. Fortunately, with the advent of improved low etch surface preparations, this should allow these ≤2.6-mil lines to be consistently producible.

I can’t speak for other shops, but in my opinion the greatest issues don’t typically lie in the ability to image these types of geometries. The larger issues are mechanical as to whether you can use the thinner copper clad materials as well as reliably etch down in between the ever-decreasing spaces between fine lines. So 4-mil lines and spaces are considered the standard nominal or “easy” product. This is quickly moving toward 3/3 as the norm.

Once again, the real challenge is not just in imaging the product. While there have been great improvements in the imaging areas with the widespread use of LDI and newer, thinner, dry film photo-resists, the larger challenge for us is typically related to the chemical etching to form the individual traces. Since most designs utilize via-in-pad to increase density and allow the use of these finer pitch components, the added copper required for via fill exacerbates the etching issues. Couple this with the increased use of sequential laminations requiring plated sub-assemblies. This extra surface plating increases the amount of copper that is required to be etched through to create the 3-mil spaces. Thus we have had to get creative in our ability to planarize and partial button plate most PCBs having these requirements. All of these added mechanical operations require precise control to minimize the impact on dimensional stability to avoid subsequent registration issues for later processes.

Obviously, controlling the amount of surface copper is paramount. Whether by careful planarization or partial plating operations.

One good thing is that by using 1.3-mil (30 µm) dry films and the use of 16kw and higher LDI equipment, the photoimaging is quite easy at this time. This makes fine lines and spaces fairly simple to produce on print and etch innerlayers if the copper cladding is fine enough. The larger issue comes when producing these types of lines/spaces on the outer layers of these packages.

When talking to designers I urge them to start with the thinnest copper readily available. Currently that would be ¼-oz. copper foil; however, on core constructions this is not always possible. I recommend avoiding sequential constructions when possible, as I’m sure most of you would if the design would allow, and finally, be aware of the added copper plating that each one of the via fill and sequential lamination cycles will add. These all work against the ability to readily realize finer lines and spaces.

Finally, the drive will always be to higher density in lines and layers. So this will effectively drive the lines and spaces down to physical or chemical limitations in the abilities to define (etch) these types of features.

This is where we are with this technology today. Not everyone can do it but most companies I know are headed in that direction. Frankly, at some point we are going to need to develop newer techniques beyond what are commonly used today.

The fact of the matter is that electronics just like the world are getting smaller all the time and we in the PCB industry are going to have to keep up and if want to support that trend.

All I can say is stay tuned for that.

John Bushie is ASC's Application Engineering Manager and is also a Process Engineering Specialist. To contact Bushie, click here.




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