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Originally presented at IPC APEX EXPO 2016 and published in the proceedings.
Introduction
The one constant in electronics manufacturing is change. Moore’s Law, which successfully predicted a rate of change at which transistor counts doubled on integrated circuits (ICs) at lower cost for decades, is ceding to be an appropriate prediction tool. Increasing technical and economic requirements, deriving from the semiconductor environment, are cascaded down to the printed circuit and in particular to the IC substrate manufacturers. This is both a challenge and an opportunity for IC substrate manufacturers, when dealing with the demands of the packaging market.
As a consequence, miniaturization of lines and spaces (L/S) down to 5/5 µm and even below to 2/2 µm in conjunction with smaller blind micro vias (BMV) is required to meet the very challenging wiring densities for new technologies. However, implications of the ‘faster, smaller, and cheaper’ mindset also affect high-end HDI printed circuit board manufacturers. The existing production infrastructure based on panel plating is not capable of 20/20 µm L/S—as required by OEMs for high-end mobile devices. As a consequence of this, production technology needs to change to pattern plating.
Miniaturization leads to increased requirements for all process steps involved in the value-added-chain. This paper discusses the corresponding challenges for metallization based on electroless copper processes. In order to minimize the effect of the differential etch process, which is one of the major factors determining surface feature resolution, the thickness of the deposited electroless copper layer on the surface of the substrate must be reduced. Moreover, the thickness at the sidewalls and bottom of the BMV must be improved to ensure excellent via filling performance.
To read this entire article, which appeared in the June 2016 issue of The PCB Magazine, click here.
