DARPA ERI stands for the Defense Advanced Research Projects Agency and the Electronics Resurgence Initiative. This tongue-twisting acronym is the latest Department of Defense (DoD) effort to catch up and surpass world semiconductor technology for the secure IC chips needed by advanced defense electronics systems. First, it is a recognition that integrated circuit technology at secure IC defense facilities is losing ground to the commercial sector—especially offshore. Second, this initiative is much more comprehensive than past efforts, and the first time I have seen some mention of electronics systems packaging (printed circuits).
The ERI was announced on June 1, 2017, with projected funding of approximately $150 billion. The ERI project rollout is in phases with newer projects building on prior successes. The whole effort is anticipated to take at least five years.
The base organization for the ERI is the Joint University Microelectronics Program (JUMP). That includes six university centers and 11 manufacturing organizations and will be funded for approximately $200 million over five years to define the needed efforts in the whole ERI.
The three initial focus areas announced were architectures, design, and materials and integration. From DARPA’s own website:
- The architectures thrust asks whether the electronics community can enjoy the benefits of specialized circuitry while still relying on general programming constructs through the proper software and hardware co-design
- The designs thrust asks whether the electronics community can dramatically lower the barriers to modern system-on-chip design and unleash a new era of circuit and system specialization and innovation
- The materials and integration thrust asks whether the integration of unconventional materials can enhance conventional silicon circuits and continue the progress traditionally associated with scaling
Overall, the ERI effort “aims to forge forward-looking collaborations among the a) commercial electronics community, b) defense industrial base, c) university researchers, and d) the DoD to create a more specialized, secure, and heavily automated electronics industry that serves the needs of both the domestic commercial and defense sectors.” The mechanism of the ERI is through project grants and is made up of phases.
Six initial awards were announced in April of 2018 with more publicity at the first ERI summit in late July 2018 in San Francisco. These were not called Phase 1 but Page 3, referring to the predictions from the original Gordon Moore 1965 paper—what to do when Moore’s law runs out of steam—in case you want to go back 53 years. Of course, everyone remembers the Moore prediction on Page 2 that transistors on chips double every 18–24 months.
Interestingly, the arrow in the center of the ERI logo (Figure 1) points to two possible semiconductor possibilities—the dotted line is the transistor density if no solutions are found to the limitations looming when Moore’s law expires, or the continued upward trend arrow of electronics based on the success of this ERI effort to advance both defense and commercial electronics.
Figure 1: DARPA’s ERI logo.
From the ERI start, a foundational program most relevant to electronic interconnection is CHIPS (Common Heterogeneous Integration and IP Reuse Strategies). The subtitle to the project is “Modular electronics systems that can leverage the best of DoD and commercial designs and technologies.” Perhaps you have heard the term “chiplets” to refer to this concept—joining standard slivers of silicon from computation, memory, I/O, and timing into a new, unique heterogeneous entity. This is envisioned to allow rapid DoD chip development. A close sister ERI design project (CRAFT) projects reducing the development time for unique defense chips from 170 weeks to 45 weeks.
Anyway, the following 17 participants in the CHIPS program have divided up into work teams: Georgia Tech, University of Michigan, North Carolina State, Cadence, Synopsys, Micross, Intrinsix, Jariet Technologies, Ferric Semicondutor, ON Semiconductor, Intel, NIST, General Electric, Raytheon, Lockheed Martin, Boeing, and Northrop Grumman. The project team organization is presented in Figure 2 (SOTA = state-of-the-art):
Figure 2: Project team organization for CHIPS.
Besides being able to use small sections of dedicated silicon in a unique circuit, CHIPS will allow different semiconductor materials to be integrated (e.g., indium phosphide, gallium nitride, gallium arsenide, etc.). And CHIPS builds from a previous, little-recognized DARPA program from 2012 called DAHI (Diverse Accessible Heterogeneous Integration). This was an initial effort to integrate various substrate materials into a combined device. Figure 3 gives a view of the opportunity for the CHIPS program.
Figure 3: CHIPS opportunity.
The ERI also authorized two Page-3 programs of interest to electronics interconnection, and under the materials thrust. The FRANC (Foundations Required for Novel Compute) program which focuses on revolutionary new materials and the 3DSoC (Three Dimensional System on a Chip) that expands semiconductor technology into the Z-direction.
Now coming to the ERI awards in 2019 is PIPES (Photonics in the Package for Extreme Scalability) for integrating photonic signaling at the chip level. Also in the award cycle is T-MUSIC (Technologies for Mixed-mode Ultra-scaled Integrated Circuits) with proposers’ day on January 19 to discuss the scope of this effort and proposal submission date—March 12. A typical Defense Broad Agency Announcement (BAA) for research project proposals consists of announcement, optional public proposers day for questions, proposal submission, and project award.
If you are now fully confused with the DARPA ERI acronym alphabet soup, there are six more designated programs in the architectures and design thrusts that I have not described here. I will only be covering these in the future if they have an impact on the electronics interconnection.
- Gordon E. Moore, “Cramming more components onto integrated circuits,” Electronics, vol. 38, no. 8, April 19, 1965.
- T-MUSIC’s submission for award
Dennis Fritz was a 20-year direct employee of MacDermid Inc. and has just retired after 12 years as a senior engineer at (SAIC) supporting the Naval Surface Warfare Center in Crane, Indiana. He was elected to the IPC Hall of Fame in 2012.