Troubleshooting process-related defects is not as simple an exercise as we would like to believe. The printed wiring board fabrication process is a complex set of mechanical and chemical processes containing multiple steps. When even one of the process steps is not in control, end results can be disastrous. Further confounding the engineer responsible for solving these issues is often the over-reliance on the belief that the defect noted in a certain process step had its genesis in that step. And this assumption is often incorrect. Experience has taught us that while the defect may be detected only after a particular process step (e.g., voids in the via after electrolytic plating), the origin of that void may have been in the PTH process or the result of poor drilling. These are just a few examples. To be successful in determining the problem and root cause identification, one must look at the defect holistically.
In a future column, I will present a few suggested approaches to problem solving and defect mitigation. For now, I present a view of some defects where at first glance the origins are not obvious.
The Case of the Etch Resist Etch-out
When voids in the PTH are detected after etching, it is quite easy to assign root cause to the etching operation. While there are no complete voids seen in Figure 1, one can surmise that the thin areas will eventually form a void or voids. While it is true that the etching operation is what is in action here, the etching process was deemed in control and there were no etch-out voids seen on other part numbers.
Take a closer look at the cross-section. What is noted first on the pads? There is a noticeable tapering of the copper indicating that the tin etch resist did not hold up to the etchant. True, the tin either was absent initially, or was of insufficient thickness to withstand the action of the etchant. In addition, there is a thinning down of the copper in the plated through-hole indicating the same. So, why can’t the engineer blame the etching operation for the condition shown in Figure 1? There is further evidence in a section shown in Figure 2.
As shown quite clearly in Figure 2, there was an issue related to the tin plating. There is sufficient thickness of copper as the plating moves down the plated through-hole.
When presented with this situation, the troubleshooting team should approach the problem-solving exercise as follows:
Available methodologies are the TQC PDCA process: Plan–Do–Check–Act; and the Six-Sigma DMAIC process: Define–Measure–Analyze–Improve–Control. Both are used in formal problem-solving exercises. Many of you are also familiar with the General Scientific Method:
- Define the question/make observations
- Gather information and facts
- Form hypothesis
- Perform experiments and collect data
- Analyze data
- Interpret data and draw conclusions
- Summarize results
In a future column, I will present a more detailed discussion of problem-solving and methodology. For purposes of this month’s column, a less formal approach is used.
The engineers and operators determined the etching process was in control. Data supports that statement. Not all part numbers processed by the fabricator exhibited this condition.
Looking back on the plating operation, samples of randomly selected part numbers not yet etched were checked for tin plating thickness. While plating thickness within the vias met minimum thickness requirements (0.30-0.35 mils), there were pads showing considerably less tin (0.12-0.15 mils); and even thinner on the knees of some holes.
Armed with this information, the team determined as a first approach to review the tin electroplating process as well as any issues in the control of the tin process. The information gathered provided the following:
- Tin plating thickness was within specification in the holes
- Tin plating thickness on some part numbers showed very thin tin on the surface (pads) but not within the vias
- Electrical connections were checked to ensure that sufficient current was flowing from the power supplies to the cathodes (the boards)
- Tin plating was non-uniform on the pads (in many cases) and very thin over the knee of some of the larger diameter vias (in most cases this occurred randomly)
Now, as a point of further information, the fabricator was using a semi-bright tin plating process. This included controlling two separate organic addition agents. One of the additives is a grain refiner and wetting agent designed to insure a more even plating distribution across the panel. The second additive is used to improve throwing power, especially in small diameter vias. Upon further analysis, it was discovered that the ratio of the two additives were out of the normal operating range. In this case, the second additive was much higher in concentration in the working plating solution. This caused the tin plating to be suppressed in areas of the board including the pads and the knees of the vias. The thin plating is then susceptible to attack by the etchant, leading to voids or, at the very least, thin copper in those areas.
While the case described here happens all too often, there are several other potential causes that will be presented in Part 3.
This column originally appeared in the March 2021 issue of PCB007 Magazine.