The Bare (Board) Truth: Stackups—Properly Conveying Your Info to the Fabricator

In this column, I will discuss how to create the perfect board stackup, specify what you truly want to convey to the fabricator, and eliminate conflicting information about stackups.

What Is a Board Stackup?
The board stackup is the Z-axis stackup showing layer configurations, all specific dielectrics, copper weights, material types, and any information regarding controlled impedances. This is critical to make sure your design works as expected but is a frequently overlooked and underrated part of your output package that is often left up to the fabricator. This can work if you don’t have any special dielectric or controlled impedance needs.

Not sharing those needs with your desired fabricator sets you up for impedance mismatches or performance variables in your design. Fortunately, a good fabricator has very experienced CAM folks who can recognize serpentine traces as single-ended (SE) structures, differential pairs as controlled structures, and CPWGs likewise as controlled structures. This should lead to an email, or at the very least, a phone call from your fabricator to clarify your stackup intent.

thompson_cartoon350.jpg1. Where to Place This Information
The Z-axis depiction of a board stackup is typically on the fab drawing, in a README file, or as a separate sheet depicting the Z-axis stackup, such as a PDF, DXF, spreadsheet, or some other type of document. It is important to remember if you call out material type, copper weights, and controlled impedance information on the fab notes, they should not conflict with what is shown on the separate stackup.

In addition, the fab notes cannot conflict with the available space on your board. For example, if you call out 1-oz inner layers and 2-oz finished outers after plate, the internal and external layer space should not exceed 0.005” or 0.125 mm, and the external layer space (copper feature to copper feature) starting on half-ounce with a 1-oz plate-up should not exceed 0.004” or 0.1 mm. This will save you a lot of grief from a fabricator calling you to tell you your chosen stackup copper weight does not support your available design space.

2. What to Call Out on Your Fab Notes and Stackup
Here is a short list of what to call out on your fab notes and possibly even on your stackup. This information should exist somewhere; whether you choose to have it on both the stackup and in the fab notes is really up to you. But again, if you choose to have the following information on both, they should not conflict with each other, such as:

  • Material type
  • Desired copper weight (as long as it does not conflict with your available space)
  • Specific dielectrics
  • Controlled impedances
  • Layer configuration

First, call out the material type. I recommend calling out your material by the 4101/# as opposed to calling out a specific material type unless directed by the end-user to do so. This can save you some time in negotiating with the board fabricator, as not all fabricators have all materials in stock or even normally carry them. Some materials, such as the Rogers 3000 and 4000 series of materials, should be built as a core-cap type construction. I would recommend calling out material by name if you have a specific function that requires said materials—things like high temp, high speed, low Dk, low loss tangents, or even the use of very thin dielectrics to take advantage of the inherent decoupling properties of thin dielectrics.

Note: Any use of thin dielectrics for this purpose should reside near the external layers and not in the center of the board stack if at all possible. If you need to call out a specific material type, consider adding a few alternatives so that whoever builds your part has a shot at having or stocking it. Having said that, some research on your part will be required to evaluate the various materials you are adding as alternatives. They should be true alternatives and consistent with your performance expectations.

Second, call out the copper weights involved. Can you mix copper weights internally? Yes. Many designs depend on the use of core material with a lighter copper weight on one side and a heavier weight on the opposite side, such as a signal side with lower space values and a plane side with higher space values.

However, you should not have a huge mismatch between copper on each side for the sheer processing of the cores through develop, etch, and strip. Something like two- or three-ounce on one side and three-eighths or half-ounce on the opposing side should be avoided, but half-ounce on the signal side and one-oz on the plane side is not at all out of the question. I may be “beating a dead horse,” so to speak, but once again, your stackup notes should not conflict with the stackup depiction. I cannot stress this enough. And, as before, the copper weight must fit your available space. Enough said.

Next, call out in the stackup any specific dielectrics but not necessarily on the fab notes as well. Specific dielectrics do not necessarily mean the part has controlled impedances. Some designs require thin dielectrics for close to the outer layers and thicker dielectrics in the middle of the stackup for performance reasons, such as having an eight-layer stackup with a stackup as a signal top, plane layer 2, signal layer 3, plane layer 4, plane layer 5, signal layer 6, plane layer 7, and then signal layer 8, increasing the distance between layers 4 and 5 and keeping layers 1, 2, and 3 and 6, 7, and 8 as thin as possible works well for both impedances and performance characteristics. Additionally, as mentioned before, the use of very thin dielectrics can work well for inherent decoupling and minimizing the amount of decoupling caps needed on the outers if used between PWR and GND layers.

Controlled Impedances
Next, I’m going to cover controlled impedances (Figure 1 and Table 1).

C_Thompson_Table.jpg

C_Thompson_Fig1.jpg

As I have said in numerous columns, first, consult your chosen fabricator to have them assist in specifying the trace widths, spaces, and dielectrics for various impedances. This ensures you won’t have to rip up and re-route your impedance tracks and potentially your component placement. I realize many folks do their own calculations, but as I have said before, as a designer, all you have to do is to get within 10% of your precalculations, and the fabricator will take it the rest of the way to get even closer to your desired impedances. Simply call out all the impedances that reside on each layer. If you use a template for this description, that is fine, but make some mention if they don’t all reside on the called out layers.

As a former fabricator, I understood that they may not exist on the design today but may exist on the design at some point in the future. Thus, when I corresponded with the customers, I would simply say we have calculated for them all but have only included calculations that reside on the design as it exists. Be sure to add a tolerance for the impedances, wide traces, such as CPWGs, on surface layers, which can have as little as ±5%. But thinner tracks for single-ended and differential pairs should have a larger tolerance like ±10%. If the part has impedances that reside on a blind plate-up layer, the fabricator may even ask for ±15%.

Lastly, layer configurations must match the description for both the layer names and the stackup. Any mismatch can cause a delay in your project. Make sure the layer names are also in sequence. For example, a 10-layer board should have layers 1–10 in sequence, not layer 1, 3, 5, and then back to layer 2, 4, etc. This could cause a serious stackup error at fabrication.

Likewise, as I said before, the layer names should be the same in the image data and the stackup. Some mismatches are tolerated and understood, such as calling out a PWR plane on the stackup and calling the actual layer +5V. This should be understood by the fabricator, but if the names aren’t even close, you should expect a phone call or email from your chosen fabricator to clarify.

Blind/Buried Via Stackups

For a blind or buried via stackup, you will want to remember a few things if you want to be able to send the stackup to just about any fab shop (Figure 2). Most fabricators can do blind/buried vias, but some have constraints on what they can do based on their process.

C_Thompson_Fig2.jpg
First, try to make the blind vias terminate on a plane layer, such as a GND or PWR layer or even a split plane, not a signal layer. (See the reason not to do this in my second point later.) Having said that, we see many high-speed and RF designs where this is a negative. Having any via stub can be an issue.

Second, avoid having signal integrity needs such as controlled impedances on a blind plate-up layer if you want to be able to send the job to any fab shop. Many fabricators process a blind or buried via scenario where they laminate the blind or burieds and then drill the scenario instead of doing controlled depth type drilling to drill said scenario after final lam. This means the layers are typically imaged and plated for the termination layer, such as a layer 2 in a blind 1-2 or layer 3 of a blind 1-3 after they have imaged/plated then laminated the blinds in the first cycle press.

Since this plate-up can have some slight copper thickness deviations after plate due to the plating process variable, they ask that you do not have the blind plate-up layer 2 or the layer 3 for an impedance layer in such a scenario as the ones described previously. If this cannot be avoided, and a controlled impedance layer must reside on a blind plate-up layer, they may ask for a higher tolerance for the impedance, such as ±15%.

Third, having a controlled impedance layer on a blind plate-up layer means that controlled dielectrics as the interface where the blind via controlled impedance resides requires a specific dielectric to achieve said impedances. This is where it gets tricky if the termination layer is controlled, as attempting to emulate a thin dielectric with prepreg between cores or foil internally for a blind scenario means you will have to consider the additional blind plate-up. This is usually a typical value of 1 additional mil of plating, reducing the thin prepreg dielectric even further and setting yourself up for high resistance shorts and an impedance mismatch.

These three things should be considered if you don’t want to pay more, increase your lead time, or live with a higher impedance tolerance. And you’ll be able to send your design to just about any fabricator.

Conclusion
These are the things on a short list of what every stackup should have. I hope this has helped. As usual, if you would like to comment on this column, please do; I greatly appreciate the feedback. I can be contacted at markt@msoon.com with your questions and comments, and, as always, thanks for reading!

This column originally appeared in the January 2021 issue of Design007 Magazine.

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2021

The Bare (Board) Truth: Stackups—Properly Conveying Your Info to the Fabricator

01-15-2021

In this column, Mark Thompson discusses how to create the perfect board stackup, specify what you truly want to convey to the fabricator, and eliminate conflicting information about stackups.

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2020

The Bare (Board) Truth: Via Basics

11-13-2020

In this month’s column, Mark Thompson addresses what vias are and what they are used for, as well as how they are used in PCB design. He also covers some criteria on pad size vs. via size for fabrication and how vias came about.

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The Bare (Board) Truth: 5 Questions About Improving Thermal Management

09-10-2020

Mark Thompson from Monsoon Solutions answers five questions about thermal management at the design and PCB levels, including how much heat a via dissipates, how to identify potential thermal issues, and more.

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The Bare (Board) Truth: ‘The Want of a Nail’ and the Butterfly Effect

02-17-2020

After exploring the Todd Rundgren song "The Want of a Nail" and the butterfly effect, Mark Thompson explains how small changes in design characteristics that happen at a PCB fabrication level can have larger consequences for the final product.

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2019

The Bare (Board) Truth: Teaching the Next Generation—An Overview of Today’s University Courses

09-05-2019

In this column, Mark Thompson focuses on the University of Washington, where he counted approximately 163 programs in their catalog of electronics courses. He shares the top 19 courses he thinks are the most valuable for emerging electronic engineers if he were to start his electronics career over again.

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The Bare (Board) Truth: Fabrication Starts With Solid Design Practices

06-20-2019

It’s a fact: Great board design is the key to a great PCB. I’m even more certain of this after spending two days in a wonderful class presented by Rick Hartley titled “Control of Noise, EMI, and Signal Integrity in High-speed Circuits and PCBs.” Several times during Rick’s presentation, I wanted to slap myself in the forehead and say, “I should have had a V-8!”

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Board Negotiations: Design Rules and Tolerances

06-03-2019

Here are several examples of how a PCB fabricator can deal with various tolerances. Let’s look at “press fit” applications for tool sizes. Typically, a given plated hole or slot is ±0.003” and a typical non-plated hole or slot is ±0.002”. So, what does the fabricator do when a plated hole is called out as ±0.002”? The simple answer is to calculate how much plating there will be in the hole barrel, and then over-drill to accommodate the ±0.002 tolerance.

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The Bare (Board) Truth: Eliminate Confusion

03-18-2019

This column will address eliminating confusion that creates remakes both from the end-user/designer and the fabrication house. Let’s say you’ve asked for a material type on your drawing that is not either readily available or used by your fabricator. Here, you should expect the fabrication house to respond quickly and have all the deviations at once for you to review. This includes any impedance width changes, material types, or copper weights to produce the part. Any deviations regarding drawing notes such as wrap plate requirements that cannot be incorporated due to insufficient space or the extra etch compensation to meet the wrap plate requirement should also be addressed.

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2018

The Bare (Board) Truth: Getting on the Same Page—A Data Story

11-26-2018

Thickness callouts for single-sided or double-sided orders are even more critical. As a fabricator, we can control the thickness of the multilayer by using different combinations of prepregs/cores. If a customer calls out a single-sided or double-sided job as 0.008”, is this the core dielectric or an overall dielectric? If 0.008” represents the core dielectric callout on a 2-ounce finished part, the final thickness would be closer to 0.013”. If the callout for 0.008” pertains to the overall finished thickness, we would need to start at a 0.004” core to finish at approximately 0.009” after plate, surface finish, and mask.

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The Bare (Board) Truth: Refining Output Data Packages for Fabricators

05-02-2018

One of the biggest issues PCB fabricators face is the completeness (or incompleteness) of the data output package we receive from customers on a new PCB. In this column, I am going to present what is needed, from a fabricator’s perspective, for a good output package and why.

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2016

The Bare (Board) Truth: Hey, They’re Just Vias—or Are They?

11-28-2016

I get this phone call once a week: “Mark, what is the smallest mechanical via that can be done by your company?” I reply, “What will the tolerance for the vias in question be?” If they say, “Oh, your standard +/-.003” tolerances,” I must tell them the min via would be around .0078” with a signal pad of at least .014” and an anti-pad of at least .018”. What if they don't have that kind of room?

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The Top 10 Ways Designers Can Increase Profits

04-19-2016

Can you truly increase profitability through PCB design practices? Mark Thompson believes you can. And it starts with a philosophy that embraces DFM techniques. Then you must be ready for the initial release to a fabricator by ensuring that you are communicating all of your specifications and needs clearly to the fabrication house so that you get an accurate quote. Let’s dive in, starting with Number 10 and working our way to the most important way a designer can increase company profits.

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2015

The Do’s and Don’ts of Signal Routing for Controlled Impedance

06-10-2015

In this column, we will once again be focusing on controlled impedance structures, both from the layout side and the simulation side. I will break them down into the sub-categories of the models they represent and the important points to remember when using the various models. I will also be asking questions such as, “Why would a fabricator ask for a larger impedance tolerance?” and “Where does the fabricator draw the line for controlling various structures?”

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The Bare (Board) Truth: Tips for Getting the Boards You Need

05-22-2015

This column is about meeting each customer's needs. Some customers' requirements are as simple as a specific definition for a fiducial size, rail tooling, or orientation feature, while other customers may require special processes. Mark Thompson offers fabricator tips that can help designers get the boards they need.

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What Will 2015 Bring?

02-25-2015

I’ve been thinking over what 2015 might look like, from my point of view at a PCB fabrication company. Let me first start out with some broad overviews of trends from 2014 that I see continuing. On my end, I certainly expect to see more RF work, more hybrid analog-digital PCBs, and more surface finishes for lead-free assemblies. And that’s just the tip of the iceberg.

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2014

Understanding the Typical CAM Process

03-19-2014

Not all board fabricators have the ability to have both CAD and CAM. You may say to yourself, "But a CAM tool should be able to do some, if not all, CAD functions," and that is true; but if you are really getting to the design level, you need to have a design team.

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The Bare (Board) Truth: Understanding the Typical CAM Process

03-19-2014

Not all board fabricators have the ability to have both CAD and CAM. You may say to yourself, "But a CAM tool should be able to do some, if not all, CAD functions," and that is true; but if you are really getting to the design level, you need to have a design team.

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2013

Qualifying Your Fabricator: Identifying Winners (and Losers)

12-24-2013

Columnist Mark Thompson writes, "Based on today's board complexities, a review should be done prior to quote to make sure no manufacturing issues occur. This is critical when it comes to things like minimum pre-preg interfaces on high-copper coil boards or jobs with unique reference planes for various impedance scenarios."

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The Bare (Board) Truth: Qualifying Your Fabricator - Identifying Winners (and Losers)

12-24-2013

Columnist Mark Thompson writes, "Based on today's board complexities, a review should be done prior to quote to make sure no manufacturing issues occur. This is critical when it comes to things like minimum pre-preg interfaces on high-copper coil boards or jobs with unique reference planes for various impedance scenarios."

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A PCB Design Potpourri

10-16-2013

In this column, Mark Thompson revisits topics covered in some of his previous columns and fleshes them out with new, updated information. Thompson says, "In this job, I truly learn something every day, and I'm happy to share a few notable nuggets with you."

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2012

The Bare (Board) Truth: I'm From CAM and I'm Here to Help

12-12-2012

In this column, Mark Thompson shows that fabricators are not necessarily meddling in your design; some of them really do want to help make your board right the first time. And he also demonstrates how patience and perseverance can go a long way with a customer!

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The Bare (Board) Truth: Tales From the Fab Shop

05-16-2012

Designers continue to create the same-net spacing violations when relying on autorouters. Surface features connected elsewhere on an internal plane may have copper pour too close to other metal features. Electrically it doesn't matter whether these features bridge, but for most fabricators, any sliver thinner than 0.003" has the potential to flake off and redeposit elsewhere. By Mark Thompson.

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Design to Fab: Making it Work

03-30-2012

A very large customer sent us two 4-layer boards riddled with differential pairs, with no information about any controlled impedances or specific dielectrics. When we asked if these were to be controlled, the customer was most appreciative and realized that some mention of the impedances, threshold and tolerance should have been made initially. When in doubt, talk to the customer!

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Mark Thompson: IPC APEX EXPO Wrap-Up

03-07-2012

It was a mostly sunny week in San Diego, where IPC APEX EXPO returned after a long absence. I thought the San Diego Convention Center was a great choice for a venue. And this year, the engineers and designers on the show floor were looking at new processes and technologies like kids in a candy store.

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2011

The Bare (Board) Truth: Slow Down and do it Right

09-21-2011

You may be tempted to cut corners in an effort to stay on schedule. But cutting corners to save time does not save anything if it results in a new rev. Let's talk about the risks associated with assuming your board house will find and be able to correct errors in your designs. You'll avoid most of these if you slow down and do it right!

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The Bare (Board) Truth: Four Common Fabrication Questions

08-03-2011

A few months ago, I covered the "10 Most Common Fab Misconceptions." In this column, I will take a similar approach and address four of the most common fabrication questions that I hear. These same questions keep popping up, over and over. But I believe I can dispel the myths surrounding these challenges, and explain their solutions.

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The Bare (Board) Truth: Scene and Heard at IPC APEX EXPO

06-01-2011

I'm always amazed at the diversity of people I see while people-watching in Vegas. And this year, we saw a great diversity of new products and processes at APEX. Some were new combinations of older technologies, while others addressed problems in a completely new, different way.

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2010

The Bare (Board) Truth: Netlist Mismatches Redux

12-01-2010

Let's start by clarifying the intent of the netlist compare. I still get requests to just "generate a netlist" based on the customer's Gerbers. As I have said, since the intent of a netlist compare is to compare the design criteria against the exported Gerber files, this would never find a mismatch.

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RoHS for Fabricators and Designers: Fact and Fiction

11-03-2010

Most of you have heard of the European Union's RoHS directive. Some people mistakenly think it's mainly an assembly problem. But how, exactly, does RoHS pertain to PCB fabricators and designers? Is RoHS-compliant the same as RoHS-compatible?

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Timing is Everything in Controlled Impedance Fabrication

07-20-2010

According to Mark Thompson, timing can make or break your controlled impedance board. With many jobs going through turnkey environments, late communication about impedance issues takes valuable time out of the fabrication process and can delay delivery of product, leaving the end-user and the turnkey assembler unhappy.

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The Bare (Board) Truth: How to Qualify Your Fabricator

06-16-2010

This column is written from the viewpoint of you, the customer. What should you look for when qualifying a fabricator? Sure, you want the company to be IPC Class 3 6012 capable and ISO-certified, and you may need them to be ITAR-certified as well. But what other criteria can help you separate the wheat from the chaff, so to speak?

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Impedance Lines: Keep Them on the Inside

03-02-2010

Keeping those impedance-controlled lines on the inside layers of a circuit board is a great idea for a number of reasons. Let's start with the facts: You'll make your fabricator and your customer very happy by remembering to keep them on the inside.

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2009

More CAM Edits Revealed!

11-24-2009

A typical CAM department makes numerous edits prior to fabrication. Today, I will elaborate on inner-layer feature CAM edits, including the addition of flow and starburst patterns and constraints for scored jobs, as well as the process for fabricating edge-plated features.

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The Bare (Board) Truth: What Happens to Your CAM Files?

07-22-2009

What does the CAM department do to your files and what does that mean to you? The following is a brief synopsis of the edits that are likely to be performed at CAM prior to fabrication.

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The Bare (Board) Truth: Basic Impedance Fab Guidelines, Part 1

06-10-2009

When we talk about signal integrity or impedance lines, there are some very basic guidelines to follow. Remember, impedance mismatches cause signal reflections, which reduce voltage and timing margins.

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