The Bare (Board) Truth: Stackups—Properly Conveying Your Info to the Fabricator

In this column, I will discuss how to create the perfect board stackup, specify what you truly want to convey to the fabricator, and eliminate conflicting information about stackups.

What Is a Board Stackup?
The board stackup is the Z-axis stackup showing layer configurations, all specific dielectrics, copper weights, material types, and any information regarding controlled impedances. This is critical to make sure your design works as expected but is a frequently overlooked and underrated part of your output package that is often left up to the fabricator. This can work if you don’t have any special dielectric or controlled impedance needs.

Not sharing those needs with your desired fabricator sets you up for impedance mismatches or performance variables in your design. Fortunately, a good fabricator has very experienced CAM folks who can recognize serpentine traces as single-ended (SE) structures, differential pairs as controlled structures, and CPWGs likewise as controlled structures. This should lead to an email, or at the very least, a phone call from your fabricator to clarify your stackup intent.

thompson_cartoon350.jpg1. Where to Place This Information
The Z-axis depiction of a board stackup is typically on the fab drawing, in a README file, or as a separate sheet depicting the Z-axis stackup, such as a PDF, DXF, spreadsheet, or some other type of document. It is important to remember if you call out material type, copper weights, and controlled impedance information on the fab notes, they should not conflict with what is shown on the separate stackup.

In addition, the fab notes cannot conflict with the available space on your board. For example, if you call out 1-oz inner layers and 2-oz finished outers after plate, the internal and external layer space should not exceed 0.005” or 0.125 mm, and the external layer space (copper feature to copper feature) starting on half-ounce with a 1-oz plate-up should not exceed 0.004” or 0.1 mm. This will save you a lot of grief from a fabricator calling you to tell you your chosen stackup copper weight does not support your available design space.

2. What to Call Out on Your Fab Notes and Stackup
Here is a short list of what to call out on your fab notes and possibly even on your stackup. This information should exist somewhere; whether you choose to have it on both the stackup and in the fab notes is really up to you. But again, if you choose to have the following information on both, they should not conflict with each other, such as:

  • Material type
  • Desired copper weight (as long as it does not conflict with your available space)
  • Specific dielectrics
  • Controlled impedances
  • Layer configuration

First, call out the material type. I recommend calling out your material by the 4101/# as opposed to calling out a specific material type unless directed by the end-user to do so. This can save you some time in negotiating with the board fabricator, as not all fabricators have all materials in stock or even normally carry them. Some materials, such as the Rogers 3000 and 4000 series of materials, should be built as a core-cap type construction. I would recommend calling out material by name if you have a specific function that requires said materials—things like high temp, high speed, low Dk, low loss tangents, or even the use of very thin dielectrics to take advantage of the inherent decoupling properties of thin dielectrics.

Note: Any use of thin dielectrics for this purpose should reside near the external layers and not in the center of the board stack if at all possible. If you need to call out a specific material type, consider adding a few alternatives so that whoever builds your part has a shot at having or stocking it. Having said that, some research on your part will be required to evaluate the various materials you are adding as alternatives. They should be true alternatives and consistent with your performance expectations.

Second, call out the copper weights involved. Can you mix copper weights internally? Yes. Many designs depend on the use of core material with a lighter copper weight on one side and a heavier weight on the opposite side, such as a signal side with lower space values and a plane side with higher space values.

However, you should not have a huge mismatch between copper on each side for the sheer processing of the cores through develop, etch, and strip. Something like two- or three-ounce on one side and three-eighths or half-ounce on the opposing side should be avoided, but half-ounce on the signal side and one-oz on the plane side is not at all out of the question. I may be “beating a dead horse,” so to speak, but once again, your stackup notes should not conflict with the stackup depiction. I cannot stress this enough. And, as before, the copper weight must fit your available space. Enough said.

Next, call out in the stackup any specific dielectrics but not necessarily on the fab notes as well. Specific dielectrics do not necessarily mean the part has controlled impedances. Some designs require thin dielectrics for close to the outer layers and thicker dielectrics in the middle of the stackup for performance reasons, such as having an eight-layer stackup with a stackup as a signal top, plane layer 2, signal layer 3, plane layer 4, plane layer 5, signal layer 6, plane layer 7, and then signal layer 8, increasing the distance between layers 4 and 5 and keeping layers 1, 2, and 3 and 6, 7, and 8 as thin as possible works well for both impedances and performance characteristics. Additionally, as mentioned before, the use of very thin dielectrics can work well for inherent decoupling and minimizing the amount of decoupling caps needed on the outers if used between PWR and GND layers.

Controlled Impedances
Next, I’m going to cover controlled impedances (Figure 1 and Table 1).



As I have said in numerous columns, first, consult your chosen fabricator to have them assist in specifying the trace widths, spaces, and dielectrics for various impedances. This ensures you won’t have to rip up and re-route your impedance tracks and potentially your component placement. I realize many folks do their own calculations, but as I have said before, as a designer, all you have to do is to get within 10% of your precalculations, and the fabricator will take it the rest of the way to get even closer to your desired impedances. Simply call out all the impedances that reside on each layer. If you use a template for this description, that is fine, but make some mention if they don’t all reside on the called out layers.

As a former fabricator, I understood that they may not exist on the design today but may exist on the design at some point in the future. Thus, when I corresponded with the customers, I would simply say we have calculated for them all but have only included calculations that reside on the design as it exists. Be sure to add a tolerance for the impedances, wide traces, such as CPWGs, on surface layers, which can have as little as ±5%. But thinner tracks for single-ended and differential pairs should have a larger tolerance like ±10%. If the part has impedances that reside on a blind plate-up layer, the fabricator may even ask for ±15%.

Lastly, layer configurations must match the description for both the layer names and the stackup. Any mismatch can cause a delay in your project. Make sure the layer names are also in sequence. For example, a 10-layer board should have layers 1–10 in sequence, not layer 1, 3, 5, and then back to layer 2, 4, etc. This could cause a serious stackup error at fabrication.

Likewise, as I said before, the layer names should be the same in the image data and the stackup. Some mismatches are tolerated and understood, such as calling out a PWR plane on the stackup and calling the actual layer +5V. This should be understood by the fabricator, but if the names aren’t even close, you should expect a phone call or email from your chosen fabricator to clarify.

Blind/Buried Via Stackups

For a blind or buried via stackup, you will want to remember a few things if you want to be able to send the stackup to just about any fab shop (Figure 2). Most fabricators can do blind/buried vias, but some have constraints on what they can do based on their process.

First, try to make the blind vias terminate on a plane layer, such as a GND or PWR layer or even a split plane, not a signal layer. (See the reason not to do this in my second point later.) Having said that, we see many high-speed and RF designs where this is a negative. Having any via stub can be an issue.

Second, avoid having signal integrity needs such as controlled impedances on a blind plate-up layer if you want to be able to send the job to any fab shop. Many fabricators process a blind or buried via scenario where they laminate the blind or burieds and then drill the scenario instead of doing controlled depth type drilling to drill said scenario after final lam. This means the layers are typically imaged and plated for the termination layer, such as a layer 2 in a blind 1-2 or layer 3 of a blind 1-3 after they have imaged/plated then laminated the blinds in the first cycle press.

Since this plate-up can have some slight copper thickness deviations after plate due to the plating process variable, they ask that you do not have the blind plate-up layer 2 or the layer 3 for an impedance layer in such a scenario as the ones described previously. If this cannot be avoided, and a controlled impedance layer must reside on a blind plate-up layer, they may ask for a higher tolerance for the impedance, such as ±15%.

Third, having a controlled impedance layer on a blind plate-up layer means that controlled dielectrics as the interface where the blind via controlled impedance resides requires a specific dielectric to achieve said impedances. This is where it gets tricky if the termination layer is controlled, as attempting to emulate a thin dielectric with prepreg between cores or foil internally for a blind scenario means you will have to consider the additional blind plate-up. This is usually a typical value of 1 additional mil of plating, reducing the thin prepreg dielectric even further and setting yourself up for high resistance shorts and an impedance mismatch.

These three things should be considered if you don’t want to pay more, increase your lead time, or live with a higher impedance tolerance. And you’ll be able to send your design to just about any fabricator.

These are the things on a short list of what every stackup should have. I hope this has helped. As usual, if you would like to comment on this column, please do; I greatly appreciate the feedback. I can be contacted at with your questions and comments, and, as always, thanks for reading!

This column originally appeared in the January 2021 issue of Design007 Magazine.



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