Quiet Power: Uncompensated DC Drop in Power Distribution Networks

One recurring question I get is how to factor the DC drop into the power distribution network design process. Whether you prefer time-domain based or frequency-domain based design approach, the DC drop on the distribution path must be considered. Here, I will walk you through some of the important options and considerations.

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To connect the source to the load, the power distribution network has a series of conductive elements (connectors, cables, PCB planes, traces and potentially also inductors, ferrite beads, current-sensing and current-limiting devices) and parallel bypass capacitors. In our typical electronic circuit, we feed our load with clean DC power with a known, regulated voltage. The active DC source in the example of Figure 1 could be a linear or switching regulator, monitoring, and keeping its average output voltage constant across its output connections. In such a scenario (Figure 2), due to the uncompensated voltage drop across the resistances of the series elements between the source and load, the voltage across the load will be less than what we wanted.

For our power distribution networks we need to start a systematic design by finding the noise budget. Figure 3 shows its elements. The vertical height of each line represents voltage with respect to the reference (we may call it ground), which is not shown; if drawn proportionally for a supply rail where the maximum voltage deviation is just a few percent of the nominal voltage, the reference line would be a few pages further down. The Vmax – Vmin range is what our load can tolerate at any given moment. If the load current changes with time, we will have some transient noise; it is represented by DV on the sketch. The purpose of the sketch is to illustrate the process of how we can calculate the DV range that is allowed for transient noise.

Istvan_Jan_Fig3_cap.jpg

The Vmax – Vmin range is not entirely available for the DV transients. The linear and switching regulators have a finite accuracy as to how accurately their nominal voltage can be set and how much it may drift over time, over the specified temperature range, due to unit-to-unit variations, changes of input voltage, etc. We call that range the set-point inaccuracy. Periodic and random deviation (PARD) captures any self-generated AC fluctuation of the DC source itself. In switching regulators, it is primarily the switching ripple on the output. In linear regulators we don’t have switching ripple, but the electronics in the regulators still has some random noise, which may be important to know for very sensitive loads. And we also have the uncompensated DC drop. We have to subtract all of these from the Vmax – Vmin range to get DV.

There are several details that are useful to keep in mind when we consider uncompensated voltage drop. The first is the obvious complication when we think about the entire flow of the design from beginning to end: when we start our design process, we don’t have any details worked out yet and still we need an input number—the uncompensated DC drop—which eventually will depend on the stackup, material choice (remember: DC and RA coppers have slightly different conductivity), component placement and layout. We need to accept the inevitable: If we try to push the envelope and make a cost-effective, lean, and optimized design, the design process will be iterative.

There is one trick, though, that may help us under some circumstances: If we know that the load current is not changing much with time, temperature or due to unit-to-unit differences, we can easily remove most of the uncompensated voltage drop even if the regulator sense point is monitoring the voltage before the voltage drop happens. As long as the voltage drop is not so huge that the regulator could not compensate for it, for the design process we can assume zero uncompensated voltage drop. With this assumption we complete the entire design and once we figure out what is the actual voltage drop beyond the sense point, we just statically raise the regulator’s output voltage by that amount.  

For cases when the DC load current may change a lot, we can use regulators with an external sense connection and route it on the board close to the load (Figure 4).

Istvan_Jan_Fig4_cap.jpg
If our design process does not include the package and our design requirements are formulated at the board-package interface, we are all set; connecting the voltage regulator sense point on the board under the package removes the majority of the uncompensated voltage drop.

Some chips have sense-point connection pins, which route out sensitive silicon areas so that we can connect to them the voltage regulator’s sense line, thus removing the uncompensated voltage drop all the way to the targeted silicon cells. This case is shown in Figure 5.

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There is one more case worth mentioning. Sometimes the switching regulator’s output ripple is too big for a sensitive load and lowering the switching ripple magnitude just by adding more capacitance on the regulator’s output is not a good option. In such cases, a downstream linear regulator or a series LC filter may be the best solution. Figure 6 shows this case. The LC filter usually adds to the DC voltage drop, so we may need to connect the regulator’s sense point further downstream after the LC filter.

Istvan_Jan_Fig7_cap.jpg

In all these cases, the lowering of the uncompensated DC drop comes with a potential problem: If we connect the regulator’s sense point further away from the regulator, the phase shift along that path may reduce the stability margin of the regulator’s feedback loop.

In extreme cases this can also happen even if we do not have an additional LC filter. As it was shown1, the DC resistance of a power rail with the bulk capacitors may produce noticeable phase shift near the crossover frequency of typical regulators. Figure 7 shows the sketch of the board layout1, Figure 8 shows the resulting difference caused by miniscule layout differences between the two PDN rails layouts.

Istvan_Jan_Fig8_cap.jpg
Note the marked difference in the two impedance profiles. Follow-on tests and analysis showed that the two power rails had systematically different phase shift at the converter’s crossover frequency due to very minor layout differences between the two sides.

If we need to supply power to more than one load with the same regulator, in lucky cases may have two nominally identical chips, drawing approximately the same current. If we have to position them far enough so that routing power through them sequentially would leave too much uncompensated voltage drop, a symmetric fork may be our best option. Such a case2 is shown in Figure 9. A single sense point symmetrically between the two loads will eliminate most of the uncompensated voltage drop.

Istvan_Jan_Fig9_cap.jpg 

In these days, professional tools can do a good job to simulate the DC voltage drop on power planes, vias and traces, so after completing the layout, it is always a good idea to check the DC drop to make sure that our design meets the requirements.

When it comes to the very fine details, several other factors may need to be considered. For instance, how do we deal with the voltage drop across a large pin field connecting a power-hungry chip? Do we need to consider the micro detail of the voltage drop across large pads of power connections? How would the simulated DC drop change if we take the non-vertical sidewalls of copper etching of printed circuit boards into account? Those could be important aspects in a high-end design and may be the subject of future articles.

And a final closing thought. For sake of simplicity, the voltage diagram of Figure 3 does not include margin; however, in a real design it is always a good idea to add the typical 10–20% margin for any unaccounted contributor. 

References

  1. “Impact of Regulator Sense-point Location on PDN Response,” DesignCon 2015.
  2. “How Spatial Variation of Voltage Regulator Output Impedance Depends on Sense Point Location,” DesignCon 2018.

 This column originally appeared in the January 2022 issue of Design007 Magazine.

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2022

Quiet Power: Uncompensated DC Drop in Power Distribution Networks

01-19-2022

One recurring question I get is how to factor the DC drop into the power distribution network design process. Whether you prefer time-domain based or frequency-domain based design approach, the DC drop on the distribution path must be taken into account. Professional tools can do a good job to simulate the DC voltage drop on power planes, vias and traces, so after completing the layout, it is always a good idea to check the DC drop to make sure that the design meets the requirements. Here, I will walk you through some of the important options and considerations.

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2021

Quiet Power: Ask the Experts—PDN Filters

07-12-2021

In recent years I have been getting a lot of questions about PDN filters from my course participants and from friends, colleagues and even from strangers. Long gone are the days when the essence of power distribution design recommendation was “place a 0.1uF bypass capacitor next to each power pin.”

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04-16-2021

In signal integrity, for high-speed signaling, high-frequency loss is usually considered a bad side effect that we want to minimize. The DC loss, on the other hand, matters much less, because in many high-speed signaling schemes we intentionally block the DC content of the signal.

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2020

Quiet Power: Be Aware of Default Values in Circuit Simulators

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2019

Quiet Power: How Much Signal Do We Lose Due to Reflections?

11-18-2019

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2018

Quiet Power: Measurement-to-Simulation Correlation on Thin Laminate Test Boards

12-19-2018

A year ago, I introduced causal and frequency-dependent simulation program with integrated circuit emphasis (SPICE) grid models for simulating power-ground plane impedance. The idea behind the solution was to calculate the actual R, L, G, and C parameters for each of the plane segments separately at every frequency point, run a single-point AC simulation, and then stitch the data together to get the frequency-dependent AC response. This month, I will demonstrate how that simple model correlates to measured data and simulation results from other tools.

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2017

Quiet Power: Causal Power Plane Models

12-13-2017

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2016

Dynamic Models for Passive Components

05-11-2016

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2015

Avoid Overload in Gain-Phase Measurements

07-01-2015

There is a well-established theory to design stable control loops, but in the case of power converters, we face a significant challenge: each application may require a different set of output capacitors coming with our loads. Since the regulation feedback loop goes through our bypass capacitors, our application-dependent set of capacitors now become part of the control feedback loop. Unfortunately, certain combination of output capacitors may cause the converter to become unstable, something we want to avoid. This raises the need to test, measure, or simulate the control-loop stability. Istvan Novak has more.

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2014

Vertical Resonances in Ceramic Capacitors

12-03-2014

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Quiet Power: Vertical Resonances in Ceramic Capacitors

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Because of their small size, we might think that structural resonances inside the ceramic capacitors do not exist in the frequency range where we usually care for the PDN. The unexpected fact is that the better PDN we try to make, the higher the chances that structural resonances inside ceramic capacitors do show up. This column tells you why and how.

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04-02-2014

In a previous column, Columnist Istvan Novak showed that poor cable shields can result in significant noise pickup from the air, which can easily mask a few mV of noise voltage needed to measure on a good power distribution rail. In this column, he looks at the same cables in the frequency domain, using a pocket-size vector network analyzer (VNA).

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Quiet Power: Checking Cable Performance with VNA

04-02-2014

In a previous column, Columnist Istvan Novak showed that poor cable shields can result in significant noise pickup from the air, which can easily mask a few mV of noise voltage needed to measure on a good power distribution rail. In this column, he looks at the same cables in the frequency domain, using a pocket-size vector network analyzer (VNA).

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In his last column, Istvan Novak looked at the importance of properly terminating cables even at low frequencies and also showed how much detail can be lost in PDN measurements when bad-quality cables are used. This month, he analyzes a step further the shield in cables.

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2013

Quiet Power: Cable Quality Matters

11-20-2013

In his August column Istvan Novak looked at the importance of properly terminating the cables that connect a measuring instrument to a device under test. He writes that we may be surprised to learn that even if the correct termination is used at the end of the cable, the measured waveform may depend on the quality of the cable used.

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01-15-2013

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2012

Quiet Power: What's the Best Method for Probing a PDN?

08-15-2012

Recently, one of Istvan Novak's friends asked him about the preferred method of probing a power distribution network: "Which probe should I use to measure power plane noise?" Although, as usual, the correct answer begins with "It depends," in this case the generic answer is more clear-cut: For many PDN measurements, a simple passive coaxial cable is better.

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Quiet Power: Will Power Planes Disappear?

04-04-2012

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2011

Be Careful with Transmission Lines in Plane Models

11-16-2011

Last month, we learned how we can determine the grid equivalent circuit parameters for a plane pair. You may wonder: Is it better to use LC lumped components in the SPICE netlist or to make use of SPICE's built-in transmission line models? In short, we can use either of them, but we need to set up our models and expectations correctly.

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Quiet Power: Simulating Planes with SPICE

10-12-2011

There are several excellent commercial tools available for simulating power distribution planes. However, you don't need a commercial tool to do simple plane analysis. You can, for instance, write your SPICE input file and use the free Berkeley SPICE engine to get result. If you want to do your own plane simulations, there are a couple of simple choice.

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Quiet Power: Does Dk Matter for Power Distribution?

08-16-2011

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2010

Do Not Perforate Planes Unnecessarily

11-03-2010

For this column, I will take a quick detour from the series on the inductance of bypass capacitors. I will devote this column to a few comments about via placement and its potentially detrimental impact on signal and power integrity when antipads heavily perforate planes.

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We finished the last Quiet Power column with a few questions about the inductance of bypass capacitors: Why do different vendors sometimes report different inductance values for nominally the same capacitor? Start by asking the vendors how they obtained these inductance values.

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Why PI Design is More Difficult Than SI

05-19-2010

Why is power integrity design more difficult than signal integrity design? Reasons abound, and unlike SI, we've only begun to study PI. Collective wisdom and experience gained over the coming years will help to alleviate the pain somewhat, but we should expect the challenge to stay with us for some time.

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Why S11 VNA Measurements Don't Work for PDN Measurements

04-14-2010

In this edition of Quiet Power, Istvan Novak continues to examine one-port and two-port vector network analyzer set-ups for PDN measurements, and other tricks and techniques for measuring impedance values below 5 milliohms.

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PDN Measurements: Reducing Cable-Braid Loop Error

02-24-2010

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Quiet Power: Calculating Basic Resonances in the PDN

01-27-2010

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