Flying probe testing is extremely popular in today’s manufacturing theatres. The main factor is cost reduction in contrast to dedicated fixtures and fixture testing. However, there are some limitations in flying probe testing when gauged against industry specifications—specifically, the use of indirect vs direct testing in Test Level C. Table 4-1 of IPC-9252B outlines the methodologies allowed over the different Test Levels. This month we will be discussing Test Level C as this level raises the most questions regarding the use of direct versus indirect test methods when testing product in the Test Level C class. First, we need to define some terms used in flying probe testing.
The term AABUS, or “As Agreed Between User and Supplier,” is used in IPC specifications where actions within a specific requirement are allowed, but require the mutual agreement between the user and manufacturer. This term is important as it amplifies the requirement for correct flow-down of customer requirements and any special allowances or deviation of the industry specifications. (See my April column regarding flow-down.)
Adjacency and Adjacency Window
The terms ‘adjacency’ and ‘adjacency window’ are used with flying probes defining the area for which the isolation test is performed. There are two types of adjacency: horizontal (line of sight) and vertical (Z-axis). As with fixture testers and parametric testing, the flying probes cannot accomplish a full parametric isolation test as they simply do not have the hardware. So the industry has accepted the practice of adjacency. How this works is that when a single net is interrogated for shorts it is tested against other nets in range or that are adjacent to that net. That range is defined as the adjacency window. The adjacency window is userdefinable, however the specification IPC-9252B has recommended 0.050” (1.27 mm) as a default value for horizontal or line of sight adjacency.
When programming for vertical adjacency, there is more information required and the window is variable. One needs the stack-up in formation as well as the core and foil thicknesses.
If the vertical adjacency window is programmed too shallow, the risk of missing shorts to the adjacent later(s) is possible. If the window is too large you risk picking up too many layers and the test may become much longer than intended. It is necessary to remember that if the adjacency window is changed it can affect the time taken during for the isolation test to be performed. This is directly proportional to the window size. As the adjacency window increases the time to perform the test increases, as the Adjacency Window will possibly pick up more net “in range.” Figure 1 illustrates how the window can affect the test based on the topography of the PCB using horizontal adjacency.
In Figure 1 we see two scenarios, scenario A and scenario B. When performing the isolation test this becomes important as the amount of measurements required during the test can be significantly different and affect time to perform the entire PCB test. In scenario A we see six different nets labeled A through F. We also see an adjacency window of .050”. What we see here is when Net A is tested for shorts, it must be tested against nets B through E. This is four measurements. You will notice that Net F is not tested to Net A. Net F does not fall within range of the adjacency window.
Now in Figure 1 Scenario B, we have the same adjacency window but in this case, we have nets shown labeled A through C. When the isolation test is performed on net A there will be only one measurement. Net A will be only tested against Net B. Net C is again not within range or inside the adjacency window and therefore is not tested against Net A. So in Figure 1 you can see that PCB density can affect the amount of measurements required to perform the isolation test and thus affecting time required.
Direct mode utilizes direct resistance measurements for all nets on the PCB. What this means is that during the continuity (opens) test all test points of the net are tested against the continuity threshold. Any net that violates the required resistance will be reported as a fault. When the isolation test (shorts) is performed, each net is probed using the required voltage and isolation parameter. One must remember that when flying probes perform the isolation test they are performing it via an adjacency window as defined previously.
When direct mode is used, each PCB will take the same amount of time to test. This is because every net will be tested for continuity and isolation the same way each time. PCB 2 will take the same time as PCB 1 as well as PCB 3 and so on.
Indirect mode (also termed indirect testing by signature comparison or discharge testing) is the method where the flying probe develops speed over direct mode testing. In this method, the machine develops a capacitive master by gathering a capacitive signature of the board and then comparing subsequent boards to it. When the first PCB of an order is tested, the machine places a reference probe or probes down on the PCB reference plane or planes. It will then use the remaining probes to read a signature from all nets and record those finding to the master. Depending on the type of machine, this may be direct capacitive measurements or capacitive “counts.”
To read the full version of this article which appeared in the May 2017 issue of The PCB Magazine, click here.