I’ve just completed the latest online PCEA California chapter meeting and presentation. There were more than 100 attending, and it was well worth it.
Are you familiar with PCEA, the Printed Circuit Engineering Association? It has evolved from the IPC’s former Designer’s Council and although it is no longer affiliated with IPC, the organization cooperates with IPC and other industry organizations and publications, including I-Connect007.
The PCEA is now an international network of engineers, designers, fabricators, assemblers, and others related to printed circuit process development. Scott McCurdy is a member of the executive board and leader of this particular chapter. The mission of PCEA is to promote printed circuit engineering as a profession by encouraging and facilitating the exchange of information and new design and process concepts through communications, seminars, and workshops. This is facilitated through a growing network of local and regional PCEA affiliated chapters, as well as the support of sponsors and those affiliates which include the IPC, I-Connect007, SMTA, EIPC, and others.
At this meeting, Scott mentioned that the group is planning in person “Lunch and Learn” events once again, hopefully in the next few months, with the ability to also attend virtually. After a brief update regarding the progress of the organization, the online stage was turned over to the speakers: Anaya Vardya, president and CEO of American Standard Circuits (ASC); John Bushie, ASC technical director; and Haris Basit, CEO of Averatek.
As someone who started his career as a PCB fab process engineer in the early 1960s, I find it interesting that many of the processes for PCB interconnects in use then are still in use today. (We had eyelets then, but hey, we also started using plated through-holes, too). What I find fascinating is that significantly improved, but related, processes are in use today. The presentations at this event described both those processes and their significant advantages. Let me provide a short but interesting highlight.
First, the new processes and materials allow for much smaller circuit geometries with even smaller geometric capabilities right around the corner. These advanced processes and chemistries allow for today’s need for ultra-high density, very high-performance PCBs, package substrates, and interposers, as well as passives (capacitors, inductors, antennas, waveguides, and vapor chambers). Additionally, there are the capabilities of much thinner, more uniform, and denser electroless deposition using the LMI process.
A process that is somewhat new to me is the use of filled and covered vias. Back in the day we had so many more discrete components that most of the vias were also mounting holes for discrete transistors, resisters, capacitors, and interconnect wires. Now there seem to be so many more types and locations for vias that it makes sense to fill them. Why via fill? Per the presentation, it was explained that a filled via:
- Allows for via-in-pad technology
- Allows microvia in pad
- Allows through-hole in pad
- Creates more space on the surface of the PCB for components (after all, today’s portable devices do so much more and yet must be smaller and lighter)
- Allows more design options for improved signal performance
In addition, the new type VI filled and covered vias provide additional advantages over the previous generations with the fill material able to be electrically and/or thermally conductive.
Overall, the need for more advanced PCBs has increased exponentially over the last few years. Here is a recap of their A-SAP process advantages that was part of the presentation.
I am sure that the audience found these presentations very interesting, as someone who has not been involved in this industry segment, I personally found them fascinating.
While there are a number of very valuable and interesting industry events upcoming, I found that this few-hour investment in time was a very high value.
Dan Feinberg is an I-Connect007 technical editor and founder of Fein-Line Associates.