As I write this column, I just completed revising and updating one of Polar’s oldest documents on impedance controlled PCBs: "An Introduction to the Design and Manufacture of Impedance Controlled PCBs with Insights into Insertion Loss." While preparing to update it, I noticed the date on the last revision was 20 years ago, in 2000.
Time flies! But the laws of physics don’t. What struck me as I updated the document was how the core principles are the same, but as geometries shrink and speeds increase, the signal comes under the influence of different physical characteristics of both the copper and the laminate. This column will focus on how important it is becoming to take DC trace resistance into account when measuring and specifying thin copper traces.
A good understanding of this topic will lead to fewer spins and also reduce the risk of going down blind alleys when searching for correlation. I have noted in previous columns how, sometimes, fabricators attempt to correlate impedance before removing the effects of DC resistance from their measurements. This can lead to erroneous conclusions about the dielectric constant (Dk) if the Dk value is set by goal-seeking to make a high reading trace correlate.
All this reminds me of a conversation at IBM in France many years ago, where the engineer in charge of signal integrity joked that many SI software packages were "Logieciels comme une usine de Gaz,” which literally translates to, "Software like a gas refinery.” Lots of gauges and levers and pipes—and intimate knowledge of the software—is needed to get a sensible result. Fortunately, the software has become simpler to use over the years, but it remains important to remember to feed the software with good input data in order to get a sensible output.
PCB impedance control is a routine specification on many boards. As geometries shrink, fabricators making TDR impedance measurements will start to see the TDR trace rising over its length. Most of the reason for this is the DC resistance of the trace. (Note that TDR traces may rise for two primary reasons: There is DC resistance in the trace, or the impedance is actually rising because the trace is tapering.)
This DC resistance effect on the trace should not be confused with the characteristic impedance of the trace itself, which is unchanging with length. Designers should ask their PCB fabricator to use a measurement technique that de-embeds (or removes) the DC resistance from the TDR measurement.
A widely accepted technique—adopted by IPC—is launch point extrapolation (LPE). This fits a line to the TDR trace and projects it back to the start of the test coupon—the launch point—where the probe and test coupon connect (Figure 1).
Why not just test at the launch point? TDR testers used for impedance measurement look at the ratio of voltage reflected from the test trace in comparison with a calibrated 50-ohm transmission line standard. At the launch point, the reflection is masked by signal aberrations caused by the interconnect itself. For this reason, test systems make the measurement further down the line over a stable section to minimize the errors introduced by aberrations at the launch.
With line widths of four mils and above, the DC resistance in the trace is so small that the trace remains flat. As traces get progressively narrower (and with thin copper), the trace will show more and more slope, introducing an error into the characteristic impedance measurement. LPE is a proven technique to remove this artifact.
Why is the DC resistance ignored? It should not be ignored, but it is a different specification from the characteristic impedance, and the two should not be lumped together. To think of this in another way, imagine a reel of coaxial cable of 50- or 75-ohm characteristic impedance with a DC resistance of one ohm per meter. Would you say the 50-ohm cable was 60 ohms if you used 10 meters? No! the cable has a 50-ohm characteristic impedance, and the resistance per meter is a separate specification.
The same is true for PCB traces. Some PCB fabricators misunderstand this and lump the two specifications together and then try to goal-seek the Dk in a field solver to achieve a correlation between measured and modeled values. This can lead to some very odd results. If the traces are very narrow, solving for Dk without removing the DC resistance can lead to “that breaks the laws of physics” results where the “solved" Dk is less than that of the resin alone.
Thus, when PCB traces are narrow (approximately sub-60 microns or with very thin foils), it is imperative that a designer mandates that the PCB fabricator should use LPE or any other valid technique to remove the DC resistance artifact from the measurement before any goal-seeking of Dk takes place. Track resistance calculators are useful for gauging how many ohms per unit length should be present.
As a designer, you need to ensure that your fabricator understands the need to remove the DC resistance on fine line traces. If you have a trace designed where the resistance is 0.25 ohms per inch or more, you should specify that the impedance should be measured on a TDR using the LPE method.
To verify which is the case, simply test by launching from opposite ends. A varying impedance will rise from one end and fall from the other, and a resistive trace will show a rising trace regardless of which end the measurement is taken.
In conclusion, even though we are fortunate now that all SI software is not like the aforementioned IBM France engineer’s amusing description of "Logieciels comme une usine de Gaz," even with today’s simpler user interfaces, software modeling tools are only as good as the raw data you feed into them.
This column originally appeared in the December 2020 issue of Design007 Magazine.