Do you have a smartphone? Most of us do. Did you know that most smartphones contain PCBs fabricated with mSAP (modified semi-additive process) technology? The ability for a fabricator to produce 35-micron feature sizes has long been taken advantage of by this consumer market segment. A handful of very high-volume fabricators specialize in this technology and serve the industry. But outside this high-volume market, SAP processes have not been widely available for other lower- to medium-volume PCB applications.
The good news is that this is changing. Fabricators now have access to both A-SAP™ (Averatek’s semi-additive process for PCB fabrication) and mSAP, and the PCB design community is just starting to scratch the surface to find creative ways for this technology development to benefit next generation electronics. Reduced size, reduced layer count, reduced lamination cycles, and dependence on stacked microvias’ increased functionality within the same footprint; the list of benefits can goes on and on.
As the PCB design community embraces the benefits of this newly available printed circuit board fabrication technique, there are, of course, many questions to be answered. This column will address some of the most frequently asked questions related to circuit layer combinations and routing as people are introduced to this new technology.
What about power and ground layers? Do all layers need to be produced with these ultra-high density feature sizes?
It is most common to use a hybrid approach utilizing both subtractive etch layers and SAP layers in the same printed circuit board stackup. Stackups do not need to be all semi-additive or all subtractive. The layers do not need to be either one technology or the other. Typically, signal layers will utilize SAP technology, often to simplify the breakout of ever smaller BGA packages, reducing the number of layers and the number of lamination cycles required for the design. Traditional subtractive etch technology can then be used for layers that contain only larger feature sizes.
Can SAP processes also produce larger feature sizes? Does the entire layer need to have the same trace and space dimension?
SAP processes can produce larger feature sizes as well. In fact, there are signal integrity benefits to these semi-additive processes that make this fabrication technique sought after, independent of the ultra-high density routing benefits.
Just a quick peek into the fabrication process: The SAP processes move the limiting factor for fabrication from the etching process to the photolithography process. Independent of the seed layer of copper selected, which may be a thin copper foil (mSAP), or an ultra-thin layer of electroless copper (SAP), the dry film resist is patterned, and electrolytic copper is then used to form the printed circuit board traces that were patterned.
The lower limits of those trace capabilities and the tolerance of the circuit traces formed vary based on the process used. The mSAP processes, even with an ultra-thin copper foil, have a seed copper layer that is considerably thicker than the electroless copper seed layer used in the A-SAP process. Because the seed layer of copper needs to be etched where it is not required, the thicker copper will take longer to etch, which impacts the trace itself. Both the line width and space need to be larger with the mSAP process and the line width tolerance will need to be greater than with the A-SAP process. While both processes provide an improved line width tolerance, the A-SAP process with thinner electroless leaves the circuit sidewalls straight with no trapezoidal effect.
Tip: Adjust your modeling software to show traces with no trapezoidal effect and investigate how this changes the numbers. In fact, this should be a topic for a future column.
Can outer layers and plated through-holes be created with SAP processes?
Yes, a PCB designer can confidently design a printed circuit board with ultra-HDI features on outer layers and connect with reliable plated through-holes using the A-SAP process. When working with mSAP, circuitry on the outer layers is most often discouraged.
Fabricators building with A-SAP have been running regular lots of material using standard D-coupons with stacked and staggered microvias to help PCB designers and OEMs feel comfortable with the reliability of the plated through-holes created with the electroless seed layer of copper I’ve explained.
What is the minimum spacing from trace to pad (external layer)?
The copper-to-copper spacing can be a cost adder in subtractive etch processes. In the semi-additive environment, this is not the case. There are a couple things to consider. First, on inner layers, this spacing could be 25 microns or below, depending on the technology being used by the PCB fabricator.
Outer layers need to take solder mask into consideration. There needs to be enough space to allow the solder mask to fully cover the trace and not expose any copper. The thickness of copper typically determines how far you need to be away from the pad. A good rule of thumb would be to use a 50-micron gap.
What do I need to know to meet a 50-ohm impedance?
First, this topic will be addressed in a future column in much more detail. But I will tease a few high-level tips here. First, be sure that the modeling tool you are using is set for straight sidewalls if you are working with a fabricator offering A-SAP. This does have an impact. Second, pay close attention to copper height. Narrow traces will have higher loss, which is a fact, but decreasing dielectric thickness and increasing copper height do mitigate that. The ability to fabricate high aspect ratio traces (taller than wide) is dependent on the SAP technology used, so be sure to work with your fabricator as your PCB design develops.
There is a lot of work being done to help educate PCB designers about this new technology. This is our opportunity to design with manufacturing and to creatively approach these new capabilities both from a fabrication perspective and a design perspective. We will continue to dive into this in future columns, but please contact me with any burning questions.
This column originally appeared in the April 2022 issue of Design007 Magazine.