3D Convergence of Multiboard PCB and IC Packaging Design


Reading time ( words)

The electronic product design process is being challenged like never before, with the need to develop feature-rich, light, compact products at a lower cost, in less time. To address these challenges, designers are combining chips and boards in new configurations, such as complex 3D stacked structures, or new packaging technologies like package-on-package (PoP) and system-in-package (SiP). They are also embedding passive and active components on inner layers, inside cavities and within the dielectric of the board stack-up.

Traditional 2D PCB design systems are used to design one PCB at a time in isolation from the other PCBs within a product, and also in isolation from the ICs, packages, and enclosure. Validating connections between the PCBs, collision checking the boards to the enclosure, and reducing interconnection distance to the ICs requires time-consuming manual operations that are error-prone and limit the potential for reuse.

A new generation of 3D multiboard product-level design tools offer major improvements by managing multiboard placement in both 2D and 3D, and enabling co-design of the chip, package and board in a single environment. Multiboard design makes it possible to create and validate a design with any combination of system-on-chips (SOCs), packages, and PCBs as a complete system. Chip-package-board co-design enables designers to optimize routability via pin assignment and I/O placement to minimize layer counts between the package, chip and board. The new design methodology makes it possible to deliver more functional, higher performing and less expensive products to market in less time.

fig1-potock.jpg

Multiboard Design Challenges

Today’s complex multiboard electronic products create design challenges, such as planning and management of interconnects at the system level. In current-generation tools, the signal verification process for a multiboard design involves exporting pin lists that include net names for each board connector and correlating the net names to the master list of net names. In many cases, it’s also necessary to manually verify each board connector’s signal name. With mechanical engineers and board designers working with disconnected systems it’s difficult, if not impossible, to intelligently manage connectivity and changes between boards. Using a spreadsheet or some other disconnected document to manage the large number of interconnects between the PCBs in the system is time-consuming and prone to error.

When mechanical engineers have inaccurate information on the electrical design or electrical engineers have inaccurate information on the mechanical design, the result in many cases is that batteries don’t fit, mounting screws create shorts against PCBs, and connectors don’t mate with packaging openings. Improper management can easily result in wasted product development time, scrapped boards and slipped schedules.

The combination of increasing capabilities, shrinking size and more complex external shapes means that electronics must increasingly consider the shape of the package while the mechanical design is more dependent than ever on the physical aspects of the internal electronics. Multi-board designs make ECAD-to-MCAD translation more difficult because of the need to communicate the position of connectors and other common points between the boards.

Yet in the current generation of tools, the collision-checking process involves exporting placement information, usually in IDF format, for each PCB to a mechanical engineer for assembly analysis. PCB design tools have continued to focus on working in 2D on one PCB at a time, with the electrical work done in 2D and then the 2D design being exported into 3D mechanical design software where the boards are positioned and checked for interference. The PCB designer is unable to, for example, position two boards on top of each other to see how they fit together. This is normally done after the board design has been exported to the mechanical design tool. Interdependencies between interlocking boards and their enclo-sure in complex products are critical.

To read this entire article, which appeared in the June 2018 issue of Design007 Magazine, click here.

Share

Print


Suggested Items

Why We Simulate

04/29/2021 | Bill Hargin, Z-zero
When Bill Hargin was cutting his teeth in high-speed PCB design some 25 years ago, speeds were slow, layer counts were low, dielectric constants and loss tangents were high, design margins were wide, copper roughness didn’t matter, and glass-weave styles didn’t matter. Dielectrics were called “FR-4” and their properties didn’t matter much. A fast PCI bus operated at just 66 MHz. Times have certainly changed.

Bridging the Simulation Tool Divide

04/12/2021 | I-Connect007 Editorial Team
Todd Westerhoff of Siemens EDA recently spoke with the I-Connect007 Editorial Team about the divide between users of high-powered enterprise simulation tools and those who need a more practical tool for everyday use, and how Siemens is working to bridge the gap. Todd also shared his views on why so many engineers do not use simulation, as well as advice for engineers just getting started with simulation tools.

Barry Olney’s High-Speed Simulation Primer

04/09/2021 | I-Connect007 Editorial Team
The I-Connect007 editorial team recently spoke with Barry Olney of iCD about simulation. Barry, a columnist for Design007 Magazine, explains why simulation tools can have such a steep learning curve, and why many design engineers are still not using simulation on complex high-speed designs.



Copyright © 2021 I-Connect007. All rights reserved.