Advanced Stackup Planning with Impedance, Delay and Loss Validation


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A typical PCB design usually starts with the material selection and stackup definition—the stackup planning or design exploration stage. How reliable are the data provided by the material vendors and PCB manufacturers? Can we use these data to predict trace width and spacing for the target trace impedance or to calculate delays or evaluate the loss budget?

PCB routing is usually done with these preliminary data. The actual stackup may be further adjusted by the PCB manufacturer together with the trace widths and spacing, to have the target impedances. This is the typical impedance-controlled process that is well established and usually produces an acceptable outcome.

But what about the losses? Can we use preliminary data to evaluate the losses and loss-related compliance metrics? Or can we just specify the target losses and rely on the manufacturers, as is done with the impedance? Let’s try to answer these questions. An EvR-1 validation board is used here as an example with the preliminary and final data—all data for this board are provided by Marko Marin from Infinera. This board was featured in our award-winning “Expectation vs. Reality” paper.  We will use Simbeor software as the stackup exploration tool to evaluate the accuracy of the characteristic impedance, delay and losses. Simbeor is selected for the stackup exploration because it is systematically validated with the measurements up to 50 GHz.

Stackup planning begins with selecting a PCB manufacturer and possible materials and defining the stackup structure. In our case, the validation board has 20 layers with 8 layers assigned for the high-speed signals as shown in Figure 1. Low-loss Panasonic Megtron6 laminate is selected to rout the high-speed interconnects. The target impedance has been specified for the PCB manufacturer, and the manufacturer has provided expected stackup structure, trace widths, and spacing adjustments to fulfill the target impedances. This is the usual case for a production board.

According to the manufacturer, the expected impedance variations should be within 8%. That is too large to expect excellent correlation up to 30 GHz for 28 Gbps NRZ links, but it may be acceptable. The board manufacturer provided stackup geometry as shown in Figure 1 on the left side, and corresponding stackup entered for the pre-layout analysis into Simbeor software is shown on the right side. Megtron6 specs provide dielectric constant and loss tangent at multiple frequencies—just one frequency data can be used to define causal wideband Debye model. The values for Dk in the Figure 1 are slightly different from the Megtron6 specs and are provided by the PCB manufacturer based upon their experience with this material.

To read this entire article, which appeared in the July 2018 issue of Design007 Magazine, click here.

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