Vertical Conductive Structures, Part 3: Design Tool Techniques


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Editor’s Note: This article is part three of a series on vertical conductive structures. Click here to read Part 1 and Part 2.

As design complexity and density increases, it sometimes requires the designer to leverage different via technologies to successfully route into larger pin count devices while maintaining the highest level of signal integrity. Using through-hole vias can take up a lot of valuable board space; moving to smaller blind vias reduces the via size but will require larger buried vias to complete the connections deeper in the board. Another costly alternative is using every layer interconnect (ELIC) technology with each layer pair having its own copper-filled, laser-drilled microvias. Stacking these microvias on top of each other between layer pairs can extend the connection between any two layers in the board. These via technologies may successfully route the design but could cause the layer count to rise, and if not done correctly, could lead to signal integrity issues.

New vertical conductive structure (VeCS) technology can reduce layer count and improve signal integrity without the need for sequential technologies. VeCS is different than traditional through-hole vias, microvias, and ELIC designs, which are more expensive and require a high number of laminations, drilling, and plating cycles to build up a reasonable number of layers. Using VeCS combines routing channels for better utilization of the channel, escaping out large pin count devices. The larger routing channels allow more routes to escape with a more reliable/solid plane reference without the swiss-cheese effect normally seen with other via technologies.

In Allegro 17.2, VeCS structures are nothing more than a mechanical symbol that can be free-placed or placed inside of a ball grid array (BGA) field to take advantage of this new routing escape technology. No major changes were required to support these new structures in Allegro PCB Designer except for a manufacturing output update to generate limited depth (blind) drill files for pins in support of VeCS-2 blind depth structures. 17.2 Padstack Editor supports by-layer keepouts as well as adjacent layer keepouts to ensure manufacturability when these structures are used in a layout. These structures are created as library objects, so they can be easily leveraged across many designs for commonly used device escapes. If a structure requires a change, it can be made in one place with all instances refreshed in the layout.

VeCS

At the moment, we distinguish two “slot” technologies: VeCS-1, where the slots go through the board, and VeCS-2, where we do multi-level blind slots (Figure 1).

Nextgin-Fig1-082319.jpgFigure 1: The front slot on the left side shows a VeCS-1, and the right shows VeCS-2.

In practice, we will see more hybrid constructions of VeCS-1 and VeCS-2 in one slot. The advantage is that we can connect GND and powers to multiple layers using VeCS-1, and the adjacent signal only connects to layer 4, for example. The VeCS-2 part of the slot creates a stubbles connection, minimizing capacitance and the dispersion of a higher speed signal.

At the moment, NextGIn Technology is very much focused on next-generation products, such as very high bandwidth applications where signal transitions between layers can be tuned such that the impedance of the vertical trace matches the impedance of the signal layer as it transits from one layer and connects to next. This enables layer transitions with minimum loss, enabling more efficient use of routing real estate compared to the ineffective and costly point-to-point routing used today using traditional via technology.

VeCS can be combined with through-hole, buried/blind vias, and microvia/HDI technology. There is no limitation. For example, a VeCS core/multilayer can be sandwiched between a set of microvias on top and bottom.

The process flow used right now is as follows:

1. Build board per standard flow.

2. Form slots (optional at mechanical drill stage): VeCS-1 and VeCS-2 from front and back.

3. Complete plating (standard).

4. Fill slots and holes (optional).

5. Form second route and bottom route.

6. Fill slots (second route).

7. Drill through-holes (optional).

8. Complete surface plating similar to a plated over-filled via (POFV).

9. Finish the panel as standard.

To read the full article, which appeared in the August 2019 issue of PCB007 Magazine, click here.

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