Siemens Collaborates with GlobalFoundries to Provide Trusted Silicon Photonics Verification
May 19, 2022 | SiemensEstimated reading time: 2 minutes
Siemens Digital Industries Software announced that its Calibre nmPlatform now enables designers to leverage the newest GlobalFoundries (GF) silicon photonics platform. GF’s next generation, monolithic platform, GF Fotonix is the first in the industry to combine its differentiated 300mm photonics and RF-CMOS features on a silicon wafer, delivering best-in-class performance at scale.
The GF Fotonix process design kits (PDKs) include Siemens’ Calibre nmDRC software for design rule checking (DRC) and Calibre® nmLVS software for layout vs. schematic (LVS) verification. Both Calibre tools are fully certified by GF, so mutual customers designing for the new GF Fotonix platform can continue to use the trusted Calibre nmPlatform for silicon photonic devices as they have used for previous offerings.
“Siemens EDA is pleased to extend our mutual solution with GF into the emerging silicon photonics market,” said Michael Buehler-Garcia, vice president of Calibre Design Solutions product management. “While silicon photonic designs and their subsequent inclusion into multi-die offerings introduce new verification complexities, these complexities are addressed in the Calibre silicon photonics design kits, which require no change to how designers traditionally use Calibre.”
GF Fotonix consolidates complex processes that were previously distributed across multiple chips onto a single chip by combining a photonic system, radio frequency (RF) components and high-performance complementary metal–oxide–semiconductor (CMOS) logic on just one silicon chip.
“Our collaboration with Siemens EDA is another example of how GF is partnering with industry leaders to deliver innovative, time-to-market solutions for our customers,” said Mike Cadigan, senior vice president for Customer Design Enablement, GF. “The combination of Siemens’ Calibre tools, for both design verification and post tape-out operation, with the GF Fotonix solution, can help designers efficiently create the powerful, flexible, and power-efficient solutions required in today’s next-generation datacenter, computing, and sensing applications.”
Silicon photonics enables companies to bring fiber optics directly into integrated circuits. However, silicon photonic devices contain curved layouts, rather than the linear Manhattan grid features found in traditional CMOS designs. Applying traditional CMOS DRC to silicon photonic layouts yields numerous false positive errors that design teams must often spend weeks tracking down. To address this challenge, GF leverages Siemens’ Calibre eqDRC™ software, which allows rule checks to use equations in place of, or in addition to, linear measurements. This helps enable more accurate results, leading to significantly fewer errors, so design teams can spend far less time and fewer resources debugging their designs.
Similarly, the curvilinear nature of photonic structures, together with the general lack of source netlists for optics, poses a challenge when performing LVS checking. Traditional IC LVS technology extracts physical measurements from well-understood electronic structures and compares them to the intended corresponding elements in the source netlist. However, with curved structures it is difficult, if not impossible, to discern where one structure begins and another ends. With the new GF Fotonix PDK with Calibre LVS, this obstacle is resolved with the use of text and marker layers to discern regions of interest.
Silicon photonic devices are often implemented in an individual die on a specific process node, then stacked and packaged with the rest of design components in multiple dies using advanced heterogeneous packaging technologies. By using the complete core Calibre offering, total verification cycle times can be greatly reduced.
Suggested Items
iNEMI Packaging Tech Topic Series: Role of EDA in Advanced Semiconductor Packaging
04/26/2024 | iNEMIAdvanced semiconductor packaging with heterogenous integration has made on-package integration of multiple chips a crucial part of finding alternatives to transistor scaling. Historically, EDA tools for front-end and back-end design have evolved separately; however, design complexity and the increased number of die-to-die or die-to-substrate interconnections has led to the need for EDA tools that can support integration of overall design planning, implementation, and system analysis in a single cockpit.
Cadence, TSMC Collaborate on Wide-Ranging Innovations to Transform System and Semiconductor Design
04/25/2024 | Cadence Design SystemsCadence Design Systems, Inc. and TSMC have extended their longstanding collaboration by announcing a broad range of innovative technology advancements to accelerate design, including developments ranging from 3D-IC and advanced process nodes to design IP and photonics.
Ansys, TSMC Enable a Multiphysics Platform for Optics and Photonics, Addressing Needs of AI, HPC Silicon Systems
04/25/2024 | PRNewswireAnsys announced a collaboration with TSMC on multiphysics software for TSMC's Compact Universal Photonic Engines (COUPE). COUPE is a cutting-edge Silicon Photonics (SiPh) integration system and Co-Packaged Optics platform that mitigates coupling loss while significantly accelerating chip-to-chip and machine-to-machine communication.
Siemens’ Breakthrough Veloce CS Transforms Emulation and Prototyping with Three Novel Products
04/24/2024 | Siemens Digital Industries SoftwareSiemens Digital Industries Software launched the Veloce™ CS hardware-assisted verification and validation system. In a first for the EDA (Electronic Design Automation) industry, Veloce CS incorporates hardware emulation, enterprise prototyping and software prototyping and is built on two highly advanced integrated circuits (ICs) – Siemens’ new, purpose-built Crystal accelerator chip for emulation and the AMD Versal™ Premium VP1902 FPGA adaptive SoC (System-on-a-chip) for enterprise and software prototyping.
Listen Up! The Intricacies of PCB Drilling Detailed in New Podcast Episode
04/25/2024 | I-Connect007In episode 5 of the podcast series, On the Line With: Designing for Reality, Nolan Johnson and Matt Stevenson continue down the manufacturing process, this time focusing on the post-lamination drilling process for PCBs. Matt and Nolan delve into the intricacies of the PCB drilling process, highlighting the importance of hole quality, drill parameters, and design optimization to ensure smooth manufacturing. The conversation covers topics such as drill bit sizes, aspect ratios, vias, challenges in drilling, and ways to enhance efficiency in the drilling department.