3D-ICs meet the demand for integration of disaggregated system-on-chip (SoC) architecture built from multiple chiplets and heterogeneous architectures such as analog, digital, optoelectronics, and non-volatile memory. They provide improved performance and area, low power consumption due to short interconnection length, and reduced signal delay. We can broadly classify 3D-ICs as transistor-level 3D integration, system-in-package (SiP) and system-on-package (SoP), and wafer-level through-silicon vias (TSV)-based 3D integration.
TSVs are the paramount interconnection structures in 3D-ICs. 3D-ICs with TSVs have a broad impact on applications that require ultra-light, small, and low-power devices to achieve high-throughput memory access and hybrid logic circuits. They serve as vertical channels for interplane communication, offering a wide range of granularity. TSVs increase the average number of connections between two dies up to 10 times compared to the chip-to-chip connections on a PCB. They improve capacitance by six times, average connection length by 200 times for 3D stacking vs. side-by-side stacking, and relative interface power between the CPU and DRAM by approximately six times.
Signal integrity (SI) implies the capability of the signal to propagate without distortion, ensuring both the clock signal timing and the quality. Accurate SI analysis ensures both functionality and regulatory compliance. There are many factors to be considered in the 3D-IC structure for reliable transmissions, including loading effect and reflection of various 3D structural elements such as limitation of high-speed signaling by capacitive loading and impedance mismatching, reflection, and crosstalk between TSVs, die-to-die vertical coupling, jitter by inter-symbol interference, vertical die-to-die EMI coupling, high-frequency noise coupling and transfer, and RF-sensitivity reduction by EMI. SI affects electromagnetic (EM) coupling as well, as the signal quality directly affects the EM interference emissions and susceptibility. The primary goal of a designer must be to abate these factors to minimize distortion. At high frequencies, even the shortest lines can have a powerful impact on the response of the signals and hamper the SI, impacting the performance of the silicon. So, every detail of each trace and interconnect is crucial to ensure that your PCB does not behave erratically.
3D-ICs using TSVs offer faster time to market, cost reduction, miniaturization, high interconnect speed, shortened path, and lower power. However, the increased number of analog effects present in the advanced process nodes create high SI challenges. TSVs are an emphatic source of coupling noise that vacillates the SI. When a voltage change occurs, the TSVs that infiltrate through the silicon carrying high-frequency signals, such as a clock signal, become the main source of coupling noise. As the power and ground network of several planes is shared, simultaneous switching noise (SSN) produced by the high-speed switching signals propagates across the planes. TSVs are connected to landing pads (LP) in metal layers. These LPs can create routing congestion that leads to increased capacitive coupling, resulting in crosstalk and SI issues.
The shorter wire length of TSVs helps in better SI performance, but the actual wire length depends on design flow steps like floor planning, placement, and routing. 3D-IC SI analysis must do a concurrent analysis of all tiers and nets as the total noise produced by a 3D interconnect can be from coupling within the same or a neighboring level. Further, with hybrid bonding technology, TSV pitches are narrowed down to single digits that increase the via and routing density, which can impose more challenges in meeting the SI specification. The performance of your final layout with TSVs has a strong reliance on the caliber of your 3D modeling-capable physical design tools used.
Traditionally, SI analysis has been performed assuming ideal power, but considering the high-speed data rates and tight margins, this is not a correct assumption. The PDN must be modeled together with the signals to get accurate behavior. A unified design environment and verification system to capture design intent upfront, higher levels of abstraction with early estimation, and floor planning is necessary to achieve convergence through test, implementation, extraction, analysis, and packaging tools with physical, electrical, and manufacturing data into a successful “signoff” flow. SI for complicated high-speed topology depends upon an accurate and realistic simulation, which requires an accurate 3D model of the interconnects and TSVs. SI analysis using a single impulse response can then be conducted. However, to get an unerring impulse response, all the system interconnect structures must be modeled accurately.
The modeling of these highly complex structures can be very challenging and time-consuming. We need the capability to perform SI analyses quickly. Legacy field solvers do not exploit the advantages of high-performance computing. The limitations in speed and capacity of legacy field solver technology need you to simplify or partition the structure into smaller segments to fit within local computing constraints. We need a tool that can overcome the technology barriers, designed to take advantage of your multi-core compute resources by parallelizing the mathematical tasks required to solve 3D structures. Achieving SI signoff requires a signoff-level accuracy tool that enables PCB and IC package designers to incorporate end-to-end, multi-fabric, and multi-board systems—from transmitter to receiver.
Brad Griffin is a product management group director for the Multiphysics System Analysis Group at Cadence Design Systems, Inc.