The Bare (Board) Truth: Via Basics

This month’s column will address what vias are and what they are used for, as well as how they are used in PCB design. I’ll also cover some criteria on pad size vs. via size for fabrication.

Introduction to Vias
But first, how did vias come about? That’s easy. The first PCBs were all through-hole components, meaning a plated hole from one side to the other, from top to bottom. When board densities became more of an issue based on available real estate, components went from a 4-pin to an 8-pin or a 12-pin connector, etc., using all through-holes to a surface-mount-type connector in an effort to use less board space. Thus, the first use of mechanical through-hole vias.

The process for this is quite simple. Based on the tolerance expressed on the drill drawing, the vias (and component through-holes) are drilled larger (typically, 0.004–0.005”) than the necessary finished hole size. If the part is a simple two-layer board, the process is as follows. The dielectric material is pulled then taken to the drilling department. Before this operation, the CAM department will specify the proper drill size to use, and a drill programmer will set up the start and stop codes using those drill sizes for the N/C drill machine.

Once drilled, the part would go through a series of cleaners and conditioners and then into a catalyst before the electroless copper stage, where the electroless copper deposition is done. The electroless stage is not an electrowinning process like electroplate and only lays down about 0.4 mils of electroless copper in the barrel of the hole and on the panel surface. This acts as a “tooth” or a bit of metal for the electroplated copper to adhere to.

The parts are then taken to an imaging department where a photoresist is applied to the panels, and the panels are imaged. Then, the image is developed and taken to the electroplating department where the now-exposed traces and pads are plated—hence the reason holes are compensated larger before the plating process. After plating, they end up at the size and within the tolerance described on the fabrication drawing.

A multilayer is slightly different. The core material is pulled and coated in the dry-film department, and the parts are also imaged. If a standard multilayer with no blind or buried vias exists (I will get into them later in this column), the process in the plating department is a develop, etch, and strip process. The image is a negative image, so where the light sees the panel, it hardens the resist, thus protecting the traces and plane layers.

IPC Standards
Why did I talk about how a fabricator processes a given hole? Let’s talk about IPC standards. However, I will not talk about Class 1 since most products are Class 2, 3, or even 3A.

In a Class 2 IPC-6012 part, both external and internal holes can have as much as 90-degree breakout and still be acceptable (Figure 1). But for Class 3 and Class 3A, the external must have a minimum of a 0.002” annular ring after drill and plate, and the internal layers must have at least 0.001” annular ring.

That means if the part needs to meet a higher class based on its function and application, you need to design the board knowing the fabricator will over-drill the plated holes approximately 0.004–0.005” over the hole’s size stated on the drill/fab drawing. A 0.008” hole with a 0.012” pad would not be acceptable, as the part will be over-drilled by 0.004–0.005”; in the case of Class 3 and Class 3A, the part must also have an additional 0.002” annular ring. Add to this that a fabricator has both a true position tolerance and a machine tolerance (normally ±0.003”), so truthfully, given Class 3 IPC-6012, the pad size should take into consideration all of these variables. Is that even feasible?


 Figure 1: IPC annular ring acceptance criteria.

Let’s say the Class 3 IPC-6012 via size is 0.008” expressed as ±0.003” tolerance. If that were true, you would need to drill the hole at approximately 0.0138”, and the machine tolerance plus the true hole position tolerance of ±0.003” would mean a 0.016–0.018” addition to the nominal hole size (again expressed as ±0.003”). Thus, the pad size would need to be 0.026”. That is not feasible in board design where real estate/board area issues exist.

This brings me to the reason I bring up the fabrication process for holes in the first place. If the holes are simply vias, for many years now, I have told our customers (in my previous life as a board fabrication guy) to call them out as ±0.003” the entire hole size. This way, a 0.008” via could be drilled at 0.008”, and no compensation or over-drill would be required. This now means a Class 3 IPC-6012 part could be as little as 0.016–0.018” for a pad size and even less if negotiated with the fabricator if they have good control of their machine and true position tolerance.

One thing I was told many years ago was, if we added up all the tolerances, we would never be able to build a PCB. Luckily, many of the tolerances cancel out each other.

What about the use of teardrops? Teardrops are simply a fillet at the junction where the trace connects to the pad. This is done so that the hole will not break out of the throat where the trace meets the pad causing a disconnect. If you have enough room on your board design, one way to mitigate the induced drill wander that occurs in a fab environment is to use teardrops. Some examples of various teardrop styles are shown in Figure 2.


Figure 2: Snowman teardrop (for obvious reasons) on the left; fillet-style teardrop on the right.

Via Types
Here, I’ll detail a variety of via types, including (1) through-hole vias, (2) blind vias, (3) buried vias, and (4) stacked and staggered vias (Figure 3).

thompson_fig3_1120.jpg1. Through-Hole Vias
These are simply vias that go from the top to the bottom layer and are through-hole plated. They are used to pass a signal from one side of the board to the other or to make interconnects in the case of a multilayer.

2. Blind Vias
These are vias that either start from the top or the bottom side and terminate on a given internal layer. They are typically used for where board space is a premium. Examples include blinds 1–2, blinds 1–5, and blinds 3–6 (6 being the bottom layer). Note that you will need a separate NC drill file for each blind via scenario.

This can typically be done 2–3 times, but normally no more than 2–3 times from a given side. The limitation is the number of plating cycles the outer layer sees. A 10-layer example would look like top to layer 2, top to layer 3, top to layer 4, bottom layer to layer 9, bottom layer to layer 8, and bottom layer to layer 7. To make more layer connections for 14-, 16-, or 18-layer boards, buried vias can be used in conjunction with the blind vias.

Types of Blind Vias

Sequential Blind Vias
The termination inner layer is processed on the core, leaving the associated outer layer as a copper sheet only to be imaged after lamination.

Controlled-Depth or Back-Drilled Vias
All the inners are processed as a normal multilayer and then laminated as normal. The connection to the inner blind layer is done with controlled-depth mechanical drilling. The drilling can drill partially into the core between layers but must not connect to the layer past the blind termination layer.

Laser Blind Microvias
Use of a laser, either Nd:YAG (neodymium-doped yttrium-aluminum-garnet) or Nd:YLF (yttrium-lithium-fluorine), can only go through very thin substrates. An infrared laser can inherently penetrate deeper but is not able to remove copper with the longer wavelength they emit.

Laser Microvias
These are typically used for high-density interconnection (HDI) designs. Due to the physical shape of a laser microvia, the depth of a given microvia is typically two or less consecutive layers deep due to the copper plating constraints of having to remove the ablated ash produced by the laser. They can be stacked or staggered, and both are additive processes. Microvias are used for higher functionality in less space, such as cellphones or tablets.

3. Buried Vias
A via is either mechanically or laser drilled between inner layers and does not extend to the surface layers (such as blind vias). They are drilled and filled (either laser or mechanically drilled). They are usually filled during the lamination process by the prepreg.

Uses of Various Vias

Via-in-Pad and VIPPO
With the extensive use of fine-pitch devices and smaller PCBs came the advent of via-in-pad structures. Via-in-pad is literally a via inside of a pad. It is first drilled, plated, or flash plated, filled with either epoxy or copper epoxy, and planarized so the surface is made flat for the assembly process. The advantage of this technology is tighter, more closely packed component placement, enhanced thermal management, and elimination of parasitic inductance and capacitance as these reduce the signal path lengths.

Via-in-pad plated over (VIPPO) is basically the same as via-in-pad with the exception that it is associated with an SMT pad, not a normal pad, such as one for a blind via. Additionally, VIPPO is also used where they will also back-drill (controlled depth drill) out the excess metal from the hole beneath the termination to an internal layer.

Thermal Vias
These dissipate heat from one side of the board to the opposite side of the board and are typically placed directly below (or as close as possible) heating elements or components that generate a lot of heat. PCBs are more conductive across the board than they are through the dielectric.

If traces are only present on the outer layers, then most of the heat is carried sideways (horizontally), and the internal core planes may be cooler. This adds thermal stitching vias connecting surface features to the internal planes and creates more conductivity that dissipates heat to the core, reducing the overall temperatures more effectively.

Stitching Vias
Via stitching uses ground coupling. The most common use for stitching vias in a plane is to ensure short return paths for signals or to help maintain a constant ground. As soon as any current starts to flow, it will cause a voltage across the copper through which it is flowing, serving to both spread the current out but also cause the ground to bounce around. Via stitching can be an effective and low-effort way to more tightly couple ground across the PCB.

Shielding Vias or Via Fences
After reading a lot of literature on shielding vias, I will paraphrase the information I found. Via fences, also known as “picket fences,” are structures to improve isolation between components that would otherwise be coupled by electromagnetic fields. They contain a row or two, or even three rows, of vias spaced close enough together to form an electromagnetic wave barrier.

Via fences can be used to shield microstrip and stripline transmission lines or functional circuits from each other. However, via fences too close to the line being guarded can degrade the isolation of the line/circuit. They can also be used around the periphery of a board to prevent electromagnetic interference with other equipment.

4. Stacked and Staggered Vias
Stacked and staggered microvias are done with a laser (Nd:YAG or Nd:YLF) exactly as described earlier. Stacked vias are literally stacked upon each other by an additive process, and staggered vias are staggered so that they do not reside directly over each other.

The advantage of stacking vias is extremely dense board designs, such as via-in-pad structures within tight-pitch BGA footprints. For this, the vias are drilled with a laser and then plated, filled, and planarized to create the interconnect. The next layer is done by laminating another layer on top of the previous via. This can typically be done 3–4 times (or more, depending upon the fabricator). Then, the surface layer is planarized (made flat) so that the PCB is flat at assembly, and no “part rocking” will occur.

In this column, I repeatedly oversimplified both the function and process for vias. Ultimately, consult your chosen fabricator for more detail on capabilities and process limitations. Thanks for reading!

Mark Thompson, CID+, is a senior PCB technologist at Monsoon Solutions Inc. To read past columns or contact Thompson, click here. Thompson is also the author of The Printed Circuit Designer's Guide to… Producing the Perfect Data Package. Visit to download this book and other free, educational titles.

This column originally appeared in the November 2020 issue of Design007 Magazine.



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