HDP User Group 2017 European Meeting Highlights Technology Progress
The splendid conference facility at the offices of Oracle, in the royal burgh of Linlithgow in West Lothian, Scotland, was the venue for the 2017 European meeting of the High Density Packaging User Group, the project-oriented consortium whose mission is to reduce costs and risks for the electronics industries by improving cooperation between system integrators, contract assembly manufacturers and suppliers in the high-density packaging development and design process, using member resources in a domain where members can gain much more by joint activities than by duplicating work in individual member companies. I was delighted and privileged to be invited once again to sit in on the open session, an intense programme of technical presentations and discussions, project reviews, status updates and new project proposals, mostly delivered in person, some from afar by WebEx link, plus two thought-provoking guest presentations.
Participants were welcomed and invited to introduce themselves by Executive Director Marshall Andrews, who then thanked Oracle for kindly hosting the meeting before handing over to Maurice Smith of Oracle who gave an interesting address about the history and current use of the landmark Linlithgow campus. Smith explained that the site was originally built with the assistance of Scottish Enterprise as part of “Silicon Glen” and was the first SUN manufacturing operation to be built outside the USA and employed 1500. He went on to describe the transition of the site as part of SUN’s global infrastructure through to engineering solutions for telecoms companies wishing to embed SUN technologies. Following the integration into Oracle in 2010 Smith described the further transition into customer-focused infrastructure incorporating five secure modular data centres each integrating multiple power and network paths.
Andrews presented Smith with a plaque acknowledging their support of HDP User Group.
The meeting was then handed over to Project Facilitator Bev Christian to moderate the project review session. Beginning with high-frequency topics, Christian himself reviewed progress on the RF Failure Detection project, which was at the definition phase. It had been observed that failure in RF circuits could occur because of mechanical changes which affected return loss, well before the incidence of complete solder joint failure, and that RF measurements of signal paths were more sensitive than standard resistance measurements to incipient conductor or solder joint failure. The project set out to determine whether RF measurement of signal loss at different frequencies could be a useful technique for the early detection of partial cracking in solder joints, long before catastrophic failure occurred. This would benefit those industry sectors concerned with high speed data and voice communications, and could possibly put a new interpretation on the term “failed solder joint” and offer an explanation 
for many “no-fault-found” field returns. He discussed the details of test vehicle design, materials and components, and the proposed experimental plan for thermally stressing the assembly whilst making comparative DC and RF measurements. The objective was to deliver a method that would allow the detection of changes in solder joints significant enough to affect RF circuit performance that might not necessarily be detected by conventional means.
High-speed signal integrity has become an issue of increasing significance and the effects of copper surface roughness on insertion loss have been extensively studied and reported. But a curious observation to come out of the recently completed HDP User Group Smooth Copper Signal Integrity project was the apparent difference in X-axis versus Y-axis roughness on the drum side of the copper foil after certain bonding treatments, resulting in different degrees of insertion loss. This had led to the High-Frequency Loss from Copper Topology project, currently in its definition phase, and reported by Oracle’s interconnect specialist Mike Freda. Established modelling methods did not take this loss effect into account and there was no quantitative data in the literature, so the project set out to reproduce the results of Smooth Copper SI project and to investigate and measure the effect of this apparent copper directionality on insertion loss. Questions to be answered were whether this observed directionality was due to the copper foil manufacturing process or the chemical cleaning and bonding treatments used during innerlayer fabrication, how it responded to different test methods for measuring losses and to what extent loss models were affected.
The topic changed to emerging technologies, with the first presentation given by Yoshi Hiroshima from Fujitsu via WebEx link from Japan, reporting on the project studying the influence of hole-wall roughness on creep fatigue in plated-through holes, which was at the idea stage. The prediction of PTH lifetime had been the subject of previous studies, but the calculation had been found to be valid only for very high levels of strain. At lower levels, the strain was mainly creep strain which did not obey the Manson-Coffin rule for fatigue-crack growth. The current project aimed to establish an accelerated equation to predict PTH lifetime and provide a better understanding of creep strain and the influence of copper plating roughness, using finite-element simulation verified by high-temperature testing. Once the typical creep characteristics had been identified and quantified, the PTH lifetime predictor equation could be augmented and its accuracy enhanced.
Continuing the emerging technologies theme, HDP User Group facilitator Jack Fisher described the Military Halogen-Free Laminate Evaluation project which was at the idea phase, the call for participation having gone out about six weeks previously. Numerous halogen-free and low-halogen laminate projects had been conducted in the past by consortia such as iNEMI and HDP User Group, but their focus had been on consumer electronics applications, and they had not addressed the reliability requirements for the military and aerospace industries. The objective of this project was to evaluate the best possible low-halogen laminates for mil/aero applications against known reliability requirements. For the OEM, the benefits would be access to a database comparing the performance of various halogen-free laminates tested to current mil/aero qualification standards, to enable designers to select the best materials for specific harsh environment, high-reliability product requirements. Material suppliers would have the opportunity to showcase their materials, measure them against competitors’ materials and to identify product strengths and weaknesses against mil/aero requirements with a focus on lead-free assembly. He discussed typical test requirements with reference to the iNEMI 2017 roadmap, and proposed test vehicle design rules and a possible test program format. The primary project deliverable would be a report to include all empirical data with analysis, conclusions and recommendations for future work. There was some discussion as to whether the military actually wanted or needed low- or no-halogen materials and the term “military” covered a very wide range of applications, with no single group responsible for defining its requirements. But the point was made that polyimide, on which the military had depended for the last generation, might be too hygroscopic for future HDI designs, and it had limitations in high-speed signal-integrity applications. So there was plenty of scope for open-minded thinking now that a wide range of thermally stable alternative materials was available.
Mike Freda returned with an update on DISC 2, the second phase of the Digital Image Speckle Correlation project. Digital image speckle correlation is a non-contact optical technique for quantitative measurement of deformation and strain, and the project was a physics-based study to determine whether it could be used to predict the differences in reliability behaviour of the stacked microvia constructions observed in the HDP User Group Multilam project. The Multilam test vehicle designs had included combinations of microvias at various pitches and various stack heights, and either stacked on top of buried vias, or offset from them. The results of Phase 1 of the DISC project had been consistent with the Multilam IST test results, which had indicated that the all-on-buried-via designs were markedly less reliable than the off-buried-via constructions. The DISC experiments had demonstrated that in the on-stack designs, the highest shear strain corresponded to the location of failure in actual tested samples, whereas for the off-stack designs there was no evidence of shear strain; instead, a large rotational moment was observed between the structures and the trace between the vias was taking the strain and preventing failures. Phase 2 was planned to start in July 2017, and would expand the scope of test vehicle design to include 2-4 stacks on 12, 18 and 24 layer constructions on two different laminate materials. This would establish additional empirical data which could be used to compare with the data from available FEM tools.
The first guest presentation came from Martyn Gaudion, managing director at Polar Instruments, and was especially relevant to the earlier discussion of the High-Frequency Loss from Copper Topology project, since it was specifically concerned with the significance of copper roughness in modelling and calculating insertion loss. Gaudion commented that during his 25 years at Polar, the company had progressed from supplying signal integrity tools for PCB fabricators to providing modelling tools for the design community, and continued to smooth the passage between PCB design and fabrication. He put a perspective on his explanation of insertion loss modelling with a quote from George Edward Pelham Box, the distinguished British statistician: “All models are wrong, but some are useful!” before describing how copper roughness could be quantified as a parameter in a transmission-line field solver. The surface of a copper conductor had a major influence on the way a high-frequency signal was carried, because of the tendency for the current to be concentrated in the outer skin. This “skin effect” became increasingly predominant as frequencies increased beyond the 10MHz level, and the rougher the copper surface the greater the insertion loss.
It was normal industry practice to roughen the surface of copper foil, both during its manufacture and during innerlayer fabrication, to promote adhesion to laminating resins, and although “low-profile” and “ultra-low profile” foils were increasing in popularity, they still had some degree of surface roughness and this had a significant influence on skin effect and hence on insertion loss. To help in choosing appropriate design rules and material parameters for frequency-dependent PCB transmission lines, it was necessary to measure the roughness and assign it a numerical value that could be used as a parameter in field-solver calculations. Historical methods based on mechanical measurement in terms of the equivalent number and depth of scratches on conductor surfaces were only valid for low frequencies. The more recent Huray model was based on a collection of spheres, resembling snowballs or cannonballs, stacked in a pyramid geometry. If the size and number of spheres were known, a roughness correction factor could be calculated and the calculation could be simplified if a single effective ball radius was assumed. Gaudion made it clear that obtaining roughness data was a challenge, and with ever-increasing frequencies there was no correct answer, only one that was useful to all parties; “Remember Mr Box!”
Returning to the HDP User Group programme the topic was assembly and lead-free projects. Marketing Director Larry Marcanti in person, together with Richard Coyle from Nokia by WebEx link, gave an update on the Harsh Use Environment Alloy Evaluation project which was at the definition phase. The project objective was to evaluate high reliability lead-free solders suitable for harsh or more severe environmental use conditions such as automotive under-the-hood, and military and defence applications for which high-silver SAC alloys were not always suitable. The project was being carried out in collaboration with iNEMI, using accelerated thermal cycling to determine the thermal fatigue performance of multiple third-generation commercial lead-free alloys. The test vehicle had been developed for original iNEMI Alloy Project and had been used in the HDP User Group SAC-Ageing2 and SAC-Ageing3 projects, from which a significant amount of alloy ATC data existed. A series of BGAs were daisy-chained to enable in situ resistance monitoring during thermal cycling.
Third generation lead-free solder alloys fell into two categories: higher reliability alloys more suited for automotive, military-defence, avionics and telecom industries, and alloys with silver content lower than SAC305, designed for better drop/shock resistance, lower processing temperatures and lower cost. The current focus of the project was to compare thermal fatigue reliability data from aggressive thermal cycling relevant to automotive and military-defence applications. The test matrix included 15 alloys plus SAC305 and SAC105 as controls, on 167 assemblies with a total of 4848 components, and the thermal cycling was being carried out at four participating laboratories.
The second part of the project was concerned with vibration and mechanical shock testing. It was acknowledged that vibration testing was a complex subject and it was important that the test was designed to evaluate alloy performance whilst avoiding board and component effects. Two approaches had been explored: the NASA test vehicle which has been used for 305 and eutectic studies, and a new design that could be simulated prior to test to give some predictability.
Michael Carano from RBP Chemical Technology called-in on WebEx to deliver his update on the Solder Joint Reliability with Surface Finishes project, which was at the definition phase. The objective was to evaluate the toughness of solder joints on boards coated with various surface finishes and assembled with large and fine-pitch components using different solder alloys. It had been decided to differentiate from earlier work by using and testing alloys in a harsh use environment, with the test vehicle from the Harsh Use Environment Alloy Evaluation. Project goals were to determine the comparative advantages and disadvantages of the PCB surface finishes under study, to identify what components and what sizes were suitable for which type of surface finishes, and the impact of board thickness and the thickness of surface finishes. The surface finishes chosen for evaluation were ENEPIG, OSP, immersion silver and direct palladium, with SAC305 and SN100CV solder alloys. Phase 1 of the project would study BGA and LGA components on thick boards, phase 2 would study CSP and QFN components on thin boards. Temperature cycling would be carried out to JESD22-A104D, -40°C to 125°C, and vibration testing to JESD22-B103B. Details of the test vehicle were being finalised, and the project was expected to transition to implementation by end of June 2017 and be completed by end of June 2018.
Yaw Obeng from National Institute of Standards and Technology called-in on WebEx with a status report on the Pitting/Crevice Corrosion project, which was at the definition stage. The background was that small defects in solder mask could expose underlying copper and provide a place for contamination to accumulate. In an extreme example, assemblies shipped from China with batteries already in place were dead-on-arrival because of circuit etch-outs corresponding with pinholes in the solder mask. There was currently no satisfactory test method for identifying such defects in solder mask; the current J-STD-004B test protocols were originally developed to identify highly ionic contaminant levels after a cleaning process and were not completely effective at identifying pitting/crevice corrosion from no-clean flux residues. The project set out to develop and validate a test method for determining the pitting/crevice corrosion potential of solder fluxes and submit it to the IPC Cleaning and Coating Committee for consideration as an additional test within J-STD-004, and to work with the committee to implement the recommendations.
The second guest presentation came from Joan Tourné of NextGIn Technology, who generated enormous interest with his VeCS “vertical conductive structures” approach to Z-axis interconnect formation, which overcame the major conductor-density limitation of established HDI technologies whilst simplifying the build-up, improving signal integrity and eliminating CAF. In the VeCS approach, the plated hole was replaced by a vertical trace or half-cylinder, giving the designer the opportunity to create more vertical connections per unit area as well as freeing up space for routing conductors. And the vertical conductors could connect to multiple internal layers as required. This was achieved using standard PCB manufacturing processes. No special equipment was required and the technology was well within the scope of any PCB fabricator with HDI capability.
The basic procedure was to form a slot by a conventional routing operation, metallise and electroplate it by standard PCB processes, then to drill into the plated slot with a larger diameter drill bit to remove the copper from the areas between the desired vertical conductors. Tool manufacturers could supply router bits designed to minimise burring, and drill-smear problems were avoided because in principle the tool was not withdrawn from the hole it had just cut but was traversed along the slot. Moreover, plating blind slots was more straightforward than plating blind holes of similar diameter and aspect ratio because of better solution penetration and less gas entrapment. Cost savings were realised as a result of reduced layer count for a given interconnection density. If necessary VeCS design features could be incorporated locally on otherwise conventional layouts, for example to overcome fan-out problems under fine-pitch array packages. A further benefit of the VeCS principle was less disruption of internal planes, again improving signal integrity. Designs were being evaluated by leading OEMs, in cooperation with selected fabricators and assemblers, and EDA vendors were beginning to incorporate VeCS layout capability into their CAD systems.
It’s not often we see a radical development in PCB interconnection technology, and such was the level of interest within the room that it would be no surprise to see a new HDP User Group project arise as an outcome of Torné’s presentation!
Back once again to the HDP User Group programme for the final topic group: PWB Technology and Design projects. And the first presentation was a call-in from Erkko Helminen at TTM, an idea-stage project to develop an ultra-thin HDI test vehicle. Ultra-thin HDI now dominated mobile and wearable designs, such as cameras, pods and watches, and future versions might resemble IC packages. But standard IPC, ANSI and JEDEC test vehicles no longer reflected form factors, density and interconnect methods, and did not capture the failure modes of fine pitch BGA technology. They did not provide adequate data for product development, and had fallen into disuse by OEMs.
So a new test vehicle was required that would reflect emerging processes, materials and designs. It was proposed to promote the use of the open source ALV-HDI test vehicle established in the previous Ultra-Thin HDI TV project, and to encourage buy-in from suppliers, fabricators, and assemblers and secure an owner for the final specification, whether IPC, ANSI, JEDEC or a Chinese standards organisation. The plan was to test thin dielectrics from three different suppliers, fabricated at three different company locations and assembled at multiple assembly shops involved. The project was still open, and additional participants were welcome to join.
Still on the materials theme, Tony Senese called-in from Panasonic Electric Works with another idea-phase project, this time for a test vehicle for characterising conductive anodic filamentation (CAF). He commented that, although that sounded straightforward, he anticipated it becoming very complicated! CAF appeared to be a function of so many possible contributing factors, some predictable, some less so, and was probably even influenced by the phase of the moon! The project would attempt to reduce design and process effects that had nothing to do with the material, and develop a test vehicle and method to allow the CAF performance evaluation to be limited to the laminate only. This would enable shorter testing time for CAF material qualification and provide inputs to international standards bodies to develop a “materials only” CAF test methodology. There were already 17 participating, including OEMs, EMS companies, laminate manufacturers, test laboratories and standards organisations.
The final presentation of the session was again on the subject of CAF, this time an idea-phase project concerned with determining a better CAF acceleration equation, described by HDP User Group facilitator, Alun Morgan. Project goals were to determine a better acceleration factor equation for CAF and quantify the effects of voltage, temperature and humidity, to enable shorter testing time for CAF material qualification, to evaluate the higher voltage requirements of the automotive sector and hopefully prove that testing at higher voltages was not necessary, and to provide inputs to update international specifications on CAF testing.
Previous work had shown that conductive anodic filament growth was a two-step process, the first being the creation of a path by hydrolysis resulting in de-bonding of the glass-to-resin interface, and the second being electrochemical growth along that pathway. If there was no pathway, there could be no electrochemical growth and hence no CAF. Therefore, commonly-used acceleration factor equations that attempted to model the process as a single step were incorrect. For example the Sun Model included a voltage term in the equation although voltage clearly had no effect on the path formation but only had an effect after the path was formed and the electrochemical cell had been set up, after which CAF growth could be expected to be directly proportional to the strength of the electric field.
So to have a good CAF acceleration equation, it was necessary to separate the two stages and be able to detect and measure the onset of CAF. A statistical Design of Experiments was proposed as a means of evaluating the interactions between temperature and humidity at constant voltage. The project was still at the idea phase, and it remained to create the project team, with participation from the automotive sector, identify materials, agree on a test vehicle stack-up, then build and test the test vehicles and complete the statistical analysis of the results.
Jack Fisher wrapped up the day’s proceedings, thanking all present for their participation, including those presenters who had been unable to attend in person but had called in with their contributions, and put out an open invitation for new project suggestions. New project proposals should include the principal idea, with a brief background statement, a problem statement describing the issues that needed to be addressed, and a potential project output, for example an HDP report or a new IPC specification.
This was the third HDP User Group’s European meeting I had been invited to attend, and although the day was long and technically intense, it offered another great learning and networking opportunity. I’ve said it before, but the spirit of community and the willingness of people and their companies to share knowledge, skills and resources to drive the technology forward never ceases to impress. Once again, thank you HDP User Group for making me so welcome.
I am grateful to Alun Morgan for allowing me to use his photographs.
