Process Engineering & Defect Prevention


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As of this writing, I have explored many topics related to specific defects that plague printed circuit board fabricators. A key underlying theme of these writings underscores the critical need of the skilled troubleshooter to get to the underlying cause or causes of the defects. Defects may “manifest” or be detected in or after a specific operation within the printed circuit board manufacturing process, but the underlying root cause may have occurred earlier (perhaps much earlier) in the process. As I have written in prior columns, I chose to present the anomaly or defect where it is most likely to be detected, then subsequently presented the most likely root causes wherever they might have been introduced. It should be noted that these examples are presented as likely starting places for the investigation of anomalies or defects presented, or the kinds of causes that might be investigated.

The troubleshooter’s task is complicated by the fact that there are many possible ways to combine or sequence the individual process steps available to achieve the desired end structure. As an example, a simple, single-lamination multilayer printed wiring board may involve 30 to 50 process steps, while a complex, multiple lamination (sequential lamination) printed wiring board, with pre- and post-machining and other mechanical operations, and selective plating processes, could involve several hundred process steps. In an ideal world, each step could be verified correct immediately during or after the process, but in practice the effect of many processes cannot be readily evaluated until the completion of many subsequent steps make latent errors visible. Much effort is and has been expended in attempts to improve this, with limited success. Thus, it remains a troublesome issue. The concern then is the defect may not manifest itself until several downstream process steps. One may refer to this as the latent defect. The impact of these latent defects is four-fold:

1. First, the detection and verification of the defect may require real time and the diversion of skilled resources—already in short supply in most lean-running modern operations.

2. Second, there is a schedule impact in today’s just-in-time operating mode, both of the process flow disruption inherent in the detection and in the verification of the defect.

To read the full version of this article which appeared in the October 2017 issue of The PCB Magazine, click here.

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