Advanced Copper Plating Process for Any Layer Via Fill Applications with Thin Surface Copper


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Abstract

Copper-filled microvias are a key technology in high-density interconnect (HDI) designs that have enabled increasing miniaturization and densification of printed circuit boards for the next generation of electronic products. Compared with standard plated through holes (PTHs), copper-filled vias provide greater design flexibility, improved signal performance, and can potentially help reduce layer count, thus reducing cost.  Considering these advantages, there are strong incentives to optimize the via filling process.

This article presents an innovative DC acid copper via fill formulation, for vertical continuous plating (VCP) applications which rapidly fills vias while minimizing surface plating. For instance, a 125 µm x 75 µm via was filled with just 10 µm copper deposited on the outer layer surfaces. X-ray diffraction studies were done to obtain information about the grain structure (texture) of the deposit. Based on determination of the Lotgering factor, the study shows that the (111) plane has a slight preference (Lotgering factor ~0.2) over other typical planes (e.g., 200, 220, and 311). X-ray diffraction (XRD), focus ion beam (FIB), and scanning electron microscopy (SEM) data show that there is no significant change in the grain structure even after the bath was aged up to 150 Ah/L. This formulation contains no harmful formaldehyde, which was classified in 2016 by the European Union as a carcinogen, thereby restricting its use in electroplating formulations. These regulations in the future, could expand into other regions as well. Therefore, having no formaldehyde is an added advantage for safe operation and waste disposal.

To read the full version of this article which appeared in the June 2018 issue of PCB007 Magazine, click here.

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