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Some people think of the PCB manufacturing process as a black box: design data goes to the manufacturer (fabrication house), and magically, the finished PCB is produced. While it may have been like that in the past—such as manufacturing in the ‘80s, which now looks archaic and sometimes unbelievable—in actuality, fabricating PCBs today is quite a ballet of processes. All of the complex steps must be taken in place and in sync to deliver a successful product. The challenge is to identify and feed back as-built testing information to help optimize the design data over time.
Today, as in years past, the OEM design is sent to the manufacturer for processing. There, the design data is massaged to produce the required PCB within the fabrication modes and methods of the manufacturer while still producing the required end product. Now, however, this same design data is also used in other processes throughout the manufacturing process in addition to creating the photo-imaging data and CNC drill/route programs.
This same design data drives other quality control processes too. There are tools and software programs in the verification processes that utilize this same customer supplied data to drive the quality control feedback loop. The design data is used to verify inner layer and outer layer circuits, such as in the AOI and AVI processes (automated optical and visual Inspection). The design data also drives electrical test (ET) processes.
Now, in the PCB manufacturing arena, the ET game has changed considerably. To close the quality feedback loop, even more checks must be included with the board design’s tooling. And the new ET results data requires new presentation methods for an efficient response from the inspectors.
Getting Here From There
Back in the ‘80s, most ET was done by means of “self-learning” a board and then comparing it to the rest of the lot; there was no such thing as netlist test. The risk was extreme with this method because the testing standard relied on a “known good board” to use as the master. If there was no gold-standard board to use, then testing had to make do with a learned comparison test on a sample from the build lot. The risk that the sample board was bad was significant, setting up the age-old “two wrongs make a right” scenario. For example, if the board had a repeating film defect that affected the entire lot, the learn comparison test for ET would have been performed on a bad board. As would be expected, when a bad board is learned and tested against an entire lot of bad boards, they all “pass.” More than once, this false-premise test data resulted in catastrophic failures at the assembler and a 100% reject back to the manufacturer.
Complicating matters in the ‘80s were the challenges of ET verification. The fixture or grid testers of the day supplied fault data in an X-Y grid coordinate system based on the test fields of the machine. The fixtures used pins that matched the footprint of the PCB and translated down to the X-Y grid where the machine learned the electrical signature of the board. When opens or shorts were detected, they were reported in the X-Y grid. This results data had to be translated by hand to identify the locations on the board where the fault was reported. This was usually done with the help of a mylar grid overlay that the inspectors placed over the board and a datum point identified on the fixture to match to the PCB. The difficulty for the inspectors was in properly identifying the locations on the PCB that the machine had reported. Multimeters or “beepers” were used to ring out the probable fault and determine whether it was an open or a short. This methodology was risky and could easily lead to misdiagnosing a fault, which would then result in an escape.
To read the full article, which appeared in the July 2019 issue of PCB007 Magazine, click here.