IPC High-reliability Forum and Microvia Summit Review, Part II


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Editor’s Note: Click here to read Part I.

The Microvia Summit on May 16 was a special feature of the 2019 event, since microvia challenges and reliability issues have become of great concern to the PCB manufacturing industry. It provided updates on the work of members of the IPC V-TSL-MVIA Weak Interface Microvia Failures Technology Solutions Subcommittee and opportunities to learn about latest developments in methods to reveal and explain the presence of latent defects, identify causes and cures, and be able to consistently and confidently supply reliable products.

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Dr. Michael H. Azarian of CALCE at the University of Maryland explored the effects of design and manufacturing factors on the reliability of microvia interconnects, discussing the relative strengths and weaknesses of blind, buried, isolated, staggered, and stacked microvias in HDI circuits. He stressed this point, “What looks like a relatively simple structure is actually associated with a vast number of design and process parameters that can impact reliability.”

Azarian began by considering quality issues associated with microvia filling by electrolytic copper plating. Incomplete filling or voiding could degrade reliability through localised stress concentration reducing fatigue life. He then showed several examples of corner cracks, barrel cracks, and interface separation, some attributed to inadequate process control, some to brittle fracture of the electroless copper.

Also, Azarian used finite element analysis to help determine the effects of microvia defects and process parameters on microvia lifetime, using fatigue modelling to simulate a series of solder reflow cycles followed by thermal cycling. He commented that the total strain range of the first solder reflow cycle was much larger than that of the second and third cycles due to work hardening of the copper. Fatigue life was affected by the size and shape of voids, and Azarian observed that small spherical voids actually increased the fatigue life, whereas for conical voids, the fatigue life decreased with the void size. Microvia aspect ratio also affected fatigue life when voids were present, and for a given conical void shape and volume ratio, the smaller the aspect ratio, the longer the microvia fatigue life. CALCE developed a second-order regression model to predict the cycles to failure of copper-filled stacked microvias under thermal loading and used finite element modelling for fracture analysis

Then, Azarian highlighted some of the challenges involved in microvia testing and the detection of delamination and cracking, particularly at the early stages of degradation. Advantage had been taken of the high-frequency skin effect to monitor interconnect degradation by observing changes in RF impedance. And time-domain reflectometry at high frequencies provided a further route to the early detection of interconnect failure.

Lance Auer from Conductor Analysis Technologies reported highlights from IPC committee meetings at IPC APEX EXPO 2019 and the movement towards performance-based acceptance testing for microvia reliability. He commented on the shortcomings of testing to existing IPC 6010-series specifications, which often did not identify the failures. There had been many examples of failures after passing all testing requirements, observed at in-circuit test after reflow, at environmental stress screening during box-level assembly, or in the field by the end customer. And traditional microsection techniques were not always capable of detecting many of these defects.

The IPC V-TSL-MVIA Weak Interface Microvia Failures Technology Solutions Subcommittee reported its findings during an open forum at IPC APEX EXPO 2019. In response, IPC issued a warning statement about post-fabrication microvia failures occurring during reflow but remaining undetectable at room temperature.

Several OEMs had been successfully screening lots with D-coupon testing per Method 2.6.27 Appendix A of IPC-TM-650, and IPC was moving away from traditional microsection evaluation towards performance-based acceptance testing. Reflow simulation testing for structural integrity during thermal stress was being added into the IPC-6012E qualification and performance specification for rigid printed boards.

Auer summarised the recommendations for performance-based acceptance testing agreed at the APEX 2019 committee meetings. He demonstrated the thermal profiles for reflow simulation and thermal shock testing and showed examples of change-in-resistance measurements corresponding to microvia failures. The suggested drawing notes described the design of IPC D-coupons, the number to be tested per manufacturing panel, the conditions for reflow simulation and acceptance criteria for change in resistance, the conditions for thermal shock and acceptance criteria for change in resistance, and the reporting of results.

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