Innovative Electroplating Processes for IC Substrates


Reading time ( words)

Abstract

In this era of electronics miniaturization, high-yield and low-cost integrated circuit (IC) substrates play a crucial role by providing a reliable method of high-density interconnection (HDI) of the chip to the board. To maximize substrate real estate, the distance between copper traces—also known as line and space (L/S)- should be minimized. Typical PCB technology consists of L/S larger than 40 µm whereas more advanced wafer-level technology currently sits at or around 2 µm L/S. In the past decade, the chip size has decreased significantly along with the L/S on the substrate. The decreasing chip scales and smaller L/S distances have created unique challenges for both the printed circuit board (PCB) industry and the semiconductor industry.

Fan-out panel-level packaging (FOPLP) is a new manufacturing technology that seeks to bring the PCB world and IC/semiconductor world even closer. While FOPLP is still an emerging technology, the amount of high-volume production in this market space provide a financial incentive to develop innovative solutions to enable its ramp-up. The most important performance aspect of the fine-line plating in this market space is plating uniformity or planarity. Plating uniformity, trace/via top planarity (which measures how flat the top of the traces), and vias are a few major features. This is especially important in multilayer processing, as nonuniformity on a lower layer can be transferred to successive layers, disrupting the device design with catastrophic consequences, such as short circuits. Additionally, a non-planar surface could also result in signal transmission loss by distortion of the connecting points (i.e., vias and traces). Therefore, plating solutions that provide a uniform, planar profile without any special post-treatment are quite desirable.

Here, we discuss innovative additive packages for direct-current copper electroplating specifically for IC substrates with capabilities such as embedded trench fill and simultaneous through-hole plating and via filling with an enhanced pattern plate. These new solutions not only offer better trace profile, but they also deliver via fill and through-hole plating. We also describe two electrolytic copper plating processes, the selection of which could be based on the via size and the dimple requirements of the application. Process I offers great via fill for deeper vias up to 80–120 µm diameter and 50–100µm deep. Process II is more suitable for shallow smaller vias 50–75 µm diameter and 30–50 µm deep.

In this article, we show that these two processes provide excellent surface uniformity and trace profile while also providing via filling and through-hole plating capabilities when controlled within given parameters. Process optimization and thermal and physical characterization of the metallization are also presented.

Introduction

The IC substrate is the highest level of miniaturization in PCB technology, providing the connection between the IC chip and the PCB. These connections are created through a network of electrically conductive copper traces and through-holes. The density of the traces is a crucial factor in terms of miniaturization, speed, and portability of consumer electronics. Trace density has grown immensely over the past few decades to meet today’s printed circuit designs, which include thin core material, fine-line widths, and smaller diameter through-holes and blind vias. The development of fan-out panel-level packaging (FOPLP) has been a topic among the microelectronics community for some time.

The main driving forces to push this new technology are cost and productivity. Traditional fan-out wafer-level packaging (FOWLP) uses a 300-mm wafer as the production vehicle because larger wafers are difficult to obtain. Therefore, the FOWLP has a limitation on the basic unit of process, thereby increasing the processing steps, manpower, and cost while also having a low yield. The advantage of using a PCB-like substrate is that manufacturers have more design flexibility and surface area compared to the wafer. As an example, a 610 x 457 mm panel has almost four times the surface area of a 300-mm wafer. Therefore, processing a panel this size drastically reduces cost, time, and processing steps. This is a huge advantage for the high-volume production market.

To read the full article, which appeared in the August 2019 issue of PCB007 Magazine, click here.

Share

Print


Suggested Items

The Advantages of Non-sludge Acid Copper Products

09/04/2019 | Barry Matties, I-Connect007
Mike Wood, technical director with Cerambus Asia Pacific, discusses the acid copper product from Cerambus Technology Inc. that doesn't generate sludge during the plating process and operates at higher production output by using higher current density. He talks about why this is important for the state of the vertical continuous plating (VCP) market in Asia, and the trends he’s seeing in that space.

The State of Plating

09/03/2019 | Marc Ladle, Viking Test Ltd.
Increasingly, PCB design technology utilises buried and blind via holes and plated via fill is also becoming more and more common. The buried and blind holes mean that the loading on the plating equipment is multiplied by the number of different inner layer connections. The same technology means that equipment needs to deal with thinner and thinner materials.

Vertical Conductive Structures, Part 3: Design Tool Techniques

08/23/2019 | Ed Hickey and Mike Catrambone, Cadence Design Systems, and Joan Tourné, Nextgin Technology
New vertical conductive structure (VeCS) technology can reduce layer count and improve signal integrity without the need for sequential technologies. VeCS is different than traditional through-hole vias, microvias, and ELIC designs, which are more expensive and require a high number of laminations, drilling, and plating cycles to build up a reasonable number of layers.



Copyright © 2019 I-Connect007. All rights reserved.