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The demand for miniaturization and higher density electronic products has continued steadily for years, and this trend is expected to continue, according to various semiconductor technology and applications roadmaps. The printed circuit board (PCB) must support this trend as the central interconnection of the system. There are several options for fine line circuitry. A typical fine line circuit PCB product using copper foil technology, such as the modified semi-additive process (mSAP), uses a thin base copper layer made by pre-etching. The ultrathin copper foil process (SAP with ultrathin copper foil) is facing a technology limit for the miniaturization due to copper roughness and thickness control. The SAP process using sputtered copper is a solution, but the sputtering process is expensive and has issues with via plating. SAP using electroless copper deposition is another solution, but the process involved is challenged to achieve adequate adhesion and insulation between fine-pitch circuitries.
A novel catalyst system—liquid metal ink (LMI)—has been developed that avoids these concerns and promotes a very controlled copper thickness over the substrate, targeting next-generation high density interconnect (HDI) to wafer-level packaging substrates and enabling 5-micron level feature sizes. This novel catalyst has a unique feature, high density, and atomic-level deposition. Whereas conventional tin-palladium catalyst systems provide sporadic coverage over the substrate surface, the deposited catalyst covers the entire substrate surface. As a result, the catalyst enables improved uniformity of the copper deposition starting from the initial stage while providing higher adhesion and higher insulation resistance compared to the traditional catalysts used in SAP processes.
This article discusses this new catalyst process, which both proposes a typical SAP process using the new catalyst and demonstrates the reliability improvements through a comparison between a new SAP PCB process and a conventional SAP PCB process.
The improvement in semiconductor density by miniaturization has progressed in recent decades as described by the famous Moore’s law—and it is still progressing today. The semiconductor components are assembled on an interposer called a package substrate. The package substrate allows those components to mount to a base printed circuit board (PCB) using inexpensive soldering technology. When the semiconductor size decreases, the package substrate size is also decreased. The related PCB feature sizes then also follow with the same scaling factor.
The semiconductor miniaturization brings significant economic and technical benefits and the semiconductor scale factor becomes the master for the associated package and PCB design. The semi-additive process (SAP) has recently been developed for fine-feature PCBs. However, this is mostly utilizing the thin copper foil base process because of concerns around copper adhesion to the base material. This article describes a new SAP utilizing chemically plated copper for the base conductor.
Figure 1: SAP process flow.
SAP Process and Base Copper
SAP is basically the same process concept using the panel pattern plating method that is commonly used in North America PCB shops. However, unlike subtractive processes, with SAP, the copper plating is selectively applied only to the pattern, resulting in thinner Cu to be etched away. The first step is the base copper preparation using a copper foil and a plated copper. The second step forms a plating resist with a negative pattern over the base copper. Then the third step plates up the circuit copper. The fourth step is the plating resist strip, and the last step is a quick etching of the unnecessary base copper (Figure 1).
The intention of this process is to get better pattern accuracy than with the subtractive process due to less copper etching. Copper etch in the PCB process is a wet process using an etching solution. The etching proceeds as an isotropic reaction and not like an anisotropic gas phase silicon etching. The isotropic etching ruins pattern accuracy due to different etching amounts between the initial area (copper top) and last area (copper bottom). Therefore, less etching provides higher accuracy of the pattern geometry. The other benefit of this process is the electrolytic plate for copper growth. It provides a shorter process time and a better economy for manufacturing.
A type of fully additive process places a permanent plating resist over the catalytically active substrate and then plates copper on the exposed catalyst to form the circuitry. This is usually plated copper utilizing electroless plating. This gives circuit uniformity, but the process time and cost are higher than the electrolytic plating method. The fully additive method can also utilize electrolytic copper deposition, but it limits the circuitry design due to the electrical connection needed for electrolytic plating and any leads for electrical connection will remain as a part of circuitry like an appendix. This could result in some parasitic elements that can disturb the circuit performance.
To read the full article, which appeared in the August 2019 issue of PCB007, click here.