Real Time with… SMTAI 2020: Technical Conference Review
SMTAI 2020, which was converted to a virtual event, took place from September 28–30. I attend every year, but since there was no keynote in the virtual format, I went straight to the technical conference. This event covered a broad range of topics related to everything in assembly. Over 90 technical presentations are available, but this report covers just some of the sessions I attended.
Hiroshi Komatsu, Connectec Japan Corporation
#150: 10-Micron Pitch Wiring and Bump on Substrate Formed by Imprinting Technology to Apply Low-Temperature Flip-Chip Bonding for Low-Temperature Bonding, and Fine-Pitch, Imprinting, CTE
The theme of this presentation was a new process for the minimum bump pitch in flip-chip bonding. It is limited by the difference in expansion or shrinkage caused by the CTE mismatch between the chip and the substrate. It has been exceedingly difficult to achieve a bonding pitch of 35 microns or less in the conventional technology using solder.
Due to this technical limitation, the integration of hetero-chips with a large number of pin count on a substrate was intensively studied using 2.5D LSIs that typically use an interposer, which stacks chips three-dimensionally using a through-silicon via (TSV). However, the manufacturing technology, such as a silicon interposer and TSV used for these 2.5D LSIs, is an expensive process.
In this study, Komatsu reported a narrow-pitch bonding technology based on low-temperature flip-chip bonding using silver conductive paste as bumps. In this technology, a conductive paste was used to simultaneously form wiring and bump with the pitch of 10 microns on the substrate by using an imprinting method and non-conductive paste dispensing, followed by flip-chip bonding and curing at 140°C to enhance the bonding strength and reduce the resistance of the conductive paste. This allows the use of organic substrates like polyimide and PET film.
To form wiring and bump with the pitch of 10 microns simultaneously on the substrate, the final wiring and bump shape is formed in advance as a master mold, and this is transferred to a replica mold to form an inverted shape. Further, a conductive paste is filled in the concavity of the replica mold and then transferred to the substrate. Three examples were shown using an organic substrate and the low-temperature bonding technique that otherwise could not be applied to packages.
Figure 1: Low-temperature FCB IoT application.
Figure 2: Low-temperature FCB process flow.
Charles Woychik, i3 Microsystems Inc.
#151: 3D Integration Using Heterogeneous System-in-Package (HSiP) Technology FOWLP, Reconstituted Wafers, Multi-Chip Module, Embedded Die
An interposer with embedded semiconductor dies and passive devices has been fabricated using a heterogeneous system-in-package (HSiP) technology to create a highly dense integrated multi-chip module (MCM) package solution. This technology is based on fan-out wafer-level packaging (FOWLP) technology, which consists of a molded core wafer having embedded devices, through mold vias (TMVs), and passive devices, along with buildup circuitry layers on both sides of the molded core wafer.
This HSIP technology can integrate multiple die and passives to achieve maximum device packing, which is molded using an epoxy-based silica filled molding compound to create a reconstituted wafer. To maintain a flat module, it is necessary to balance the amount of Cu in both the front and back layers to achieve the neutrality of the module bow during thermal excursions. To create the buildup layers, a first dielectric material is deposited over the reconstituted wafer, vias are created, and then the Cu circuitry is formed. This new process was provided in detail.
This sequential process is repeated until the required number of layers is formed. This same process is repeated on the backside of the wafer. After the buildup layers are produced on the molded wafer, the individual modules are diced out of the wafer. On both sides of the outer layers are ball-grid array (BGA) pads, which allow these modules to be stacked using conventional solder attach methods. Reliability testing was conducted on the new HSIP of 1,000 thermal cycles, including 0–100°C and -40–125°C.
Figure 3: The future is stacked FOWLP.
Figure 4: Test vehicle design, single slice.
Yoshinori Ejiri, Hitachi Chemical Ltd.
#154: Cu Paste for Molded Interconnect Devices Low-Temperature Metallization, Nanomaterials, Molded Interconnect Devices (MIDs), 2D Substrate, 3D Substrate
Ejiri works in R&D, downsizing and reducing the weight of electronic components by using the molded interconnect device (MID) process. The MID process has become increasingly important over the past few years. MID has been introduced as an important and accurate method of developing 3D electronic parts.
This work is concerned with Cu paste for MID, and he explained the development status of Cu paste, along with its low-temperature curing. To allow the use of thermoplastic as the base materials—that is PET, polycarbonate, polypropylene, and liquid crystal polymers—Ejiri developed a low-temperature solder paste and a coating material to increase adhesion. To increase the density of the Cu paste using printing, he explained their use of aerosol jet printing that allows geometries smaller than 140 microns while maintaining thickness to permit a lower resistance of the traces.
Figure 5: New process.
Figure 6: Cu wiring on 3D material (LCP).
Glenn Farris, Universal Instruments Corporation
#553: Building a Better, Brighter, LED Headlamp With Top-Side Alignment
Farris presented an engaging talk on the emerging and exciting trend in the automotive industry: the adoption of advanced LED headlamp lighting systems. These systems drive challenging placement requirements for LED packages. In this presentation, he showed a review of these unique challenges and discussed a novel approach to high-accuracy placement of LED packages enabling a scalable production solution: the proprietary top-side assembly placement (TAP) process.
Some of the challenges include:
- Automotive LED headlamps require precise alignment of LED emitting feature(s)
- Requires precise placement to assembly features (tooling holes) and to other LEDs under SMT process conditions
- LED position within its packaging does not meet assembly performance criteria X,Y, and Theta
- Standard SMT assembly is based on lead to pad, not a device top-side feature
After the TAP process is presented in detail (and how it addresses these challenges), then he presented a case study where they implemented TAP for a high-accuracy LED headlamp applications, including a thorough analysis of the results before and after each step.
Figure 7: Introduction to TAP.
The challenge with this type of assembly is that the LED must be precisely aligned with its lens, but the device is aligned to the package leads. The TAP process corrects this type of challenge.
Optical parts placement objectives include:
- Achieve LED placement accuracy within ±25 micron accuracy post-reflow
- Use of two drill holes on each circuit for alignment reference
- Placement accuracy measured from a reference hole on each circuit
- Pick-and-place of typical SMT devices for LEDs to mimic the process
- Baseline accuracy
- LED placement accuracy on a glass plate
- LED placement accuracy verification on panel
- Dry assembly no-wet process
- Adhesive and solder paste pre- and post-reflow
- Solder paste printing and inspection
- Low-temperature cure adhesive dispensing
- AOI for solder print characterization
- Reflow profile setup
- X-ray for void inspection
- AOI accuracy measurement
- Cross-section test
The case study showed the alignment reliability, as well as measurements of the soldering quality.
Figure 8: The TAP process flow utilizing an Inspection station to measure device to package.
Paul Wang, Ph.D., Mitac International Corporation
#554: Contact Interconnect Challenges and Resolution, Part 2: Cable and Connector Contact Interconnect Integrity in Enterprise Server for DC Application Contact interconnect, De-Assert, PSU, Contact Reliability, Contact Impedance, Mating and Un-Mating Force
This article was the second part of a series of studies on the new generation of electronic contact challenges and component interconnects technology for high-end computer products. These products include computer server and data storage for cloud computing applications at the data center, as well as core routers for service providers, edge and branch routers for enterprise networking companies, and small switch and wireless router for commercial and small and home office. All these cloud computing products require high data speed in terabytes per second and high signal integrity for the massive mobile users and IoT application whenever and wherever they wish to connect.
To achieve such mobility and signal integrity, the major focus is to see electrical interconnections between the CPU/GPU and component and contact interconnect between PSU and MB header in the system. Due to the large number of edge-card connections such as DIMM, PCIe, etc. are designed into modern computer systems, in part one of the study, a new generation of dual-contact interconnect methodology, component level contact configuration, and interconnect reliability were assessed.
Figure 9: Dual-contact interconnection and the importance of a new plating process.
Michael Ford, Aegis Software
#558: How The New IPC Digital Twin Standard Impacts Manufacturing Digital Twin, Digital Thread, IIoT, CFX, DPMX, Digital Shadow, Industry 4.0
The new IPC digital twin standard (IPC-2551) defines an interoperable framework in which thousands of applications from multiple sources work seamlessly together, providing the opportunity for "virtual prototyping" of all aspects of design, manufacturing, and beyond. The use of IPC-2551 prevents companies in all areas of the industry from making the mistake of tying themselves to any monopolistic data exchange technology.
The IPC digital twin as a standard is quite distinct from what has been seen until now in the form of proprietary solutions and technologies that offer a very small part of the overall digital value and are not easily interoperable. Since it’s built, in part, on existing IPC standards, such as IPC-2581 (DPMX), IPC-2591 (CFX), and IPC-1782 internal and external (secure supply chain) traceability, current solutions can quickly employ and connect standard digital twin modular components, creating true interoperability and real-time solution collaboration.
Figure 10: Standards create interoperability.
Ford’s presentation explains the IPC digital twin standard structure and components, using some specific use-case examples that illustrate the value and opportunity that the standard provides, exchanging digital models omni-directionally between design, manufacturing, and product lifecycle. This presentation will be of critical interest to all of those involved in design, manufacturing, and product management, including business leaders, engineers, and technology providers.
Figure 11: Digital confusion (aka “solutions”) creates a “digital tower of Babel.”
Vahid Akhavan, Ph.D., NovaCentrix
#567: Use of Flash Lamps to Achieve Non-Equilibrium Soldering and Assembly Utilizing Conventional SAC Alloys Flash Lamps, Photonic Soldering, Low-Temperature substrate, Non-Equilibrium Heating
The drive to enhance human interactivity and reduce the weight of electronic systems has led to the use of non-conventional substrates. As the substrates become thinner and more flexible and economical, the thermal stability of the working substrate is significantly lowered.
As such, the conventional modes of component attachment are no longer functional. To bridge this gap, anisotropic adhesives and tapes, as well as low-temperature solders and conductive epoxies, have been developed. However, in terms of performance, conventional soldering is still the champion. One way to combine traditional soldering techniques with thermally sensitive substrates is laser soldering. However, technical challenges, combined with the high costs of lasers, continue to create barriers to broader adoption.
Dr. Akhevan’s discussion focused on photonic soldering, which uses high-intensity flash lamps to overcome the disadvantages of laser soldering while still enabling soldering on a wide range of substrates. Similar to laser soldering, photonic soldering utilizes selective absorption of light to enable conventional solders (such as SAC305) to affix commercial packages (such as transistors, LEDs, or resistors in traditional sizes) on the underlying thermally unstable substrate (such as PET, PEN or TPU).
The very rapid (2–6 seconds) localized heating minimizes the component temperature rise, allowing the soldering of components that would be sensitive to a reflow oven. And it minimizes the local temperature of the substrate allowing newer, lower-cost films and thermoplastics to be employed as a substrate, like PVC, PP, LCP, polyester, PET, PEN, or TPU.
Figure 12: The PulseForge photonic soldering tool.
Figure 13: The value of photonic soldering is just now being explored.
Dennis Lee, NVIDIA Corporation
#750: Anatomy of the Ongoing Reliability Test (ORT) Process.
Dennis Lee is a Senior Product Reliability Engineer at NVIDIA. Lee outlined the ongoing reliability test (ORT) process and described in detail how it can be implemented in the electronics industry. The process is an extension of the FMEA procedure done in design. The paper provided a comprehensive perspective on how the ORT process can be defined, implemented, and executed.
As the industry’s approach to the ORT process is quite open-ended and inconsistent, a variety of implementations are used that may cause some confusion. The ORT process is presented as a structured and consistent approach, retaining the freedom and flexibility to define the highly customizable process, depending on product needs and quality targets. He explains the purpose, objectives, justification, and value, along with suitable methods of selecting samples and stress regiments of the ORT process. As ORT is often viewed as an optional process, Lee provides a rationale on its applicability and suitability is offered, along with guidance on the implementation decision process.
Figure 14: The ORT process.
Zohair Mehkri, Flex International
#754: How Quantum Computing Will Revolutionize Manufacturing
Mehkri explained quantum computing very simply in 20 minutes. Today's world operates in 0 and 1. This binary phenomenon has allowed for much advancement since the beginning of information technology and computer science. However, as with anything, it has had its limitations.
At a crossroads of quantum physics, computer science, and information theory, a new wave of computing is emerging from the depths of quantum study and computer science labs. Quantum computing has been studied for decades, but advances in modern science have enabled this technology to progress in the last several years more than the decades before it.
Quantum computing, at a very high level, uses qubits instead of bits and allows for multiple states to occur as opposed to just two (0 and 1). This allows for many more possibilities than standard computing. Introducing this concept into manufacturing opens doors that were never thought possible and encourages every company in this space to change computing forever.
This paper explained the concepts of quantum computing, how the technology works, and proceeded to describe its significance in the world of manufacturing, state its advantages and shortcomings, and offer a realistic view of what is perceived to occur. Since quantum computing should be powerful, it will probably be used in the cloud and with AI software.
Figure 15: Quantum computing states.
Lars Boettcher, Fraunhofer IZM Berlin
#653: PCB Embedding Technology for 5G MIMO Antenna Modules
The rollout of 5G networks has already started worldwide. In the near future, it is expected to dramatically reshape the wireless communication implementation landscape. Nevertheless, a number of technical challenges still need to be addressed in the most recent packaging development approaches, such as the implementation of a large number of connections at high data rates exhibiting high gain to compensate for the high free space loss at millimeter-wave frequencies.
Within the European funded project SERENA, partners from academia, research, and industry are collaborating to address these topics and develop an integration platform, based on PCB embedding technology, capable of reducing size, power consumption, and design time and complexity, while at the also achieving increased performance, energy efficiency, and transmitted output power.
In particular, PCB embedding technology offers the potential to realize an integrated RF electronics module containing ICs for RF signal generation and antennas with very short interconnects in a single package, minimizing the signal path losses. In the framework of the SERENA project, new RF materials suitable for the embedding of components are applied in combination with high-gain GaN and SiGe dies for the first time to implement a scalable SiP operating at 39 GHz.
Different concepts for the realization of RF modules with embedded GaN and SiGe dies are outlined, and first demonstrators are currently being fabricated at Fraunhofer IZM to develop a process technology which allows using RF laminate and prepreg materials to embed the dies for modularization and handle non-standard die pad metallization, such as 3-micron Au pads, within the embedding process sequence.
Test structures were also fabricated for the electrical assessment of the package configuration and the applied technology tested. Specifically, package interconnects, and integrated patch antenna arrays were designed, simulated with the aid of a 3D full-wave simulator, and measured after fabrication. It was shown that the interconnects realized in the PCB embedding technology have good RF properties in terms of insertion loss and return loss and are well suited for SiP RF modules. The antennas also exhibit good radiation characteristics in terms of gain and efficiency.
Figure 16: The motivation for embedding for RF applications.
Figure 17: Chip embedding process.
Sean Fleuriel, MacDermid Alpha Electronic Solutions
#654: PIT Resistant Acid Copper Electroplating Process for Flash Etching Flash Etching, V-Pit, Pitting, Via Fill, Through-Hole, Pattern Plating, Metallization
The challenges of rapidly changing products and applications for electronics continually push the requirements for IC substrates and PCBs. The industry responds with technologies, such as HDI, semi-additive processing (SAP), and modified SAP (mSAP), to meet the requirements of tomorrow. These technologies help maximize PCB real-estate usage by allowing fabricators and designers to perform multilayer buildup.
During this process, multiple metallization and etching steps are required to achieve the desired designs. With an increasing number of layers, the chance for critical defects to occur increases. Hence, a great deal of attention has been paid to the Cu deposit and how it reacts to subsequent etching processes.
Higher technologies may require many etching steps. Variations in the etching rate across the surface can result in pits forming. These defects cause severe reliability issues in the final product. Fabricators are currently trying to resolve these issues by baking the plated panels for several hours, which increases the process cost and negatively affects production output.
Therefore, innovative Cu electroplating solutions are required to produce Cu deposits that etch consistently. The purpose of this study was to investigate the underlying mechanism of pitting and to develop an innovative process to reduce pit formation. The electrolytic process also needed to be robust enough to perform consistently in large scale production.
Figure 18: Etching steps can lead to V-pit formation. Pits can cause failures in finished products.
Carmichael Gugliotti, MacDermid Alpha Electronic Solutions
#655: Single-Step Metallization Process for the Filling of Through-Holes With Copper Pulse Plating, Through-Holes, Copper-Filled, Thermal Management
Gugliotti’s paper discusses a copper plating process capable of filling through-holes with solid copper in one step for applications, such as core layer through-hole filling with minimal surface copper buildup for HDI technologies and thermal management of heat-sensitive electronics. The advantages of the single-step filling process benefit both the technology and the fabricator regarding the copper through-hole filling for the core.
Figure 19: New single-step through-hole filling.
Gerry Partida, Summit Interconnect
#902: Microvias: Is Your Product Reliability at Risk?
Partida’s presentation reviewed concerns and reliability testing of micro vias. He provided an overview of the HDI process and presented the use of current test methods and the superiority of testing with IPC-D-coupon and IPC-TM-650 test methods 126.96.36.199 and 2.6.27. He also discussed the warning statement in the forthcoming IPC-6012E (Qualification and Performance Specification for Rigid Printed Boards).
To emphasize his proposition, Partida presented test data from actual orders that showed that only these new IPC standards could detect all latent microvia defects. The higher temperatures of lead-free reflow are the main causes of this type of defect, and only four-wire testing at these temperatures will reveal them.
Figure 20: Detecting latent microvia failures in test.
Chris Hunrath, Insulectro
#905: Z-Axis Interconnects—Transient Liquid Phase Sintering (TLPS) Materials
Low-temperature liquid phase sintering (TLPS) metallurgy makes Z-axis interconnects during the lamination process rather than after. This allows for changes in the buildup sequence while having more freedom in via placement. This also opens up design possibilities and often simplifies fabrication.
Hunrath’s presentation provides a brief overview of the paste technology (what makes this possible), its manufacturing process, and some stackup examples that include high layer counts, high density interconnects, and the elimination of back drill with improved signal performance. TLPS has been used successfully by OEMs for the last 20 years to improve yields and allow for the mixing of materials in the same multilayer structure.
Figure 21: TLPS paste process overview.