# Brooks' Bits: How Many Vias Does It Take To…?

Sounds like the opening words of a bad joke. Well, here’s the answer, and it’s no joke: One! That’s right. No matter how much current you are putting down the trace, all you need is a single via. And a small one, at that.

OK, that last statement might not be true in EVERY single case. But it is true in a LOT more cases than you think. I will explain why in this column.

During 2015, I enjoyed a very productive collaboration with Dr. Johannes Adam, from Leimen, Germany. That collaboration resulted in several papers, but one in particular is relevant for this column, “Via Currents and Temperatures.” In that paper, we used a simulation tool, thermal risk management (TRM), developed by Dr. Adam, to simulate current flowing through a via and then determine the temperature of the via. The conventional wisdom is that the conducting cross-sectional area of the via should be the same as (or greater than) the cross-sectional area of the trace (conductor.) IPC 2152 explicitly endorses this:

The cross-sectional area of a via should have at least the same cross-sectional area as the conductor or be larger than the conductor coming into it. If the via has less cross-sectional area than the conductor, then multiple vias can be used to maintain the same cross-sectional area as the conductor.

But our results contradicted this; they suggested that the temperature of the via was controlled by the trace, and as long as the trace was sized correctly, any old (single) via was good enough.

If there was ever a result that cried out “show me,” this was it.

So I set out on a path to build a test board, test it, and verify the simulation results. This type of study would not have been possible without the cooperation of several people and organizations. In particular, I want to thank my longtime partner Dave Graves (now with Monsoon Solutions in Bellevue, Washington) for helping prepare the final artwork for the test board. C-Therm Technologies (Fredericton, New Brunswick) graciously measured the thermal conductivity of the board material to facilitate the simulation. And a special thanks to Prototron Circuits of Redmond, Washington, who provided the test boards and also the microsectioning work and measurements. And my collaborator on trace thermal issues, Johannes Adam, continues to be a great help in evaluating results.

Figure 1 illustrates the relevant portion of the test board. There are two 0.5 oz. test traces, each six inches long, each consisting of two, three-inch segments (top and bottom) connected by a single 10 mil diameter via. The via is plated to approximately one ounce. One test trace is 27 mil wide, providing approximately the same cross-sectional area as the conducting area of the via. The other trace is 200 mil wide. It is important to note that the vias are identical for the two traces.

To read this entire article, which appeared in the March 2016 issue of The PCB Design Magazine, click here.

## What Happens When You Assume?

07/05/2022 | I-Connect007 Editorial Team
What is design with manufacturing and what does true DWM look like in operation? In this interview, I-Connect007 columnist Dana Korf explains what it will take to achieve total communication among all the stakeholders in the PCB development cycle. He also stresses the need for everyone involved in PCB design and manufacturing to stop making assumptions, even at the risk of being labeled as “that guy” who asks too many questions.

## Book Excerpt: 'The Printed Circuit Designer’s Guide to… High Performance Materials,' Chapter 2

06/03/2022 | I-Connect007 Editorial Team
Chapter 2 of 'The Printed Circuit Designer’s Guide to… High Performance Materials' explores the varieties of woven glass fabrics and their components, and why spread glass is in such high demand for high-speed digital PCB designs. Download this book for a clearer picture of what to know when selecting which material that is most desirable for upcoming products, and obtain a solid knowledge base for making material selection decisions.

## Altium Invests in Future Designers

04/13/2022 | Andy Shaughnessy, Design007 Magazine
While at IPC APEX EXPO, I stopped by the Altium booth to visit with Rea Callender, vice president of education at Altium. Rea shared information about the company’s recent design competition for students around the world, as well as a new curriculum that is drawing interest from some unique locations.